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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: may 2005 document no. 15879 - 4 data sheet GS1503 features ? complies with smpte 292m and smpte 299m ? single chip hd embedded audio solution ? operates as an embedded audio multiplexer or demultiplexer ? full support for 48khz synchronous 24-bit audio ? support for 8 channels of audio per device ? cascadable architecture supports up to 16 audio channels ? integrated scrambler/descrambler and word alignment ? crc error detection and insertion ? audio control packet insertion and extraction ? arbitrary data packet insertion and extraction ? 3.3v power supply with 5v tolerant i/o ? 144 pin lqfp package applications hd sdi embedded audio description the GS1503 is a highly integrated, single chip solution for embedding/extracting digital audio streams into and out of high definition digital video signals. the GS1503 supports insertion/extraction of 24-bit synchronous audio data with a 48khz sample rate. audio signals with different sample rates may be converted to 48khz by using audio sample rate converters before or after the GS1503. each GS1503 supports all processing required for embedding/extracting up to eight digital audio channels in the horizontal ancillary data space of the video chroma channel. two GS1503?s can be cascaded for insertion/ extraction of up to 16 audio channels with no external glue logic. the GS1503 supports embedd ing/extracting of audio control and arbitrary data pack ets in the horizontal ancillary data space of the video luma channel. it also supports line crc detection and insertion. the GS1503 supports hd vi deo standards at 74.25mhz and 74.25/1.001mhz rates. it has an on chip smpte compliant scrambler/de-scram bler, and integrated word alignment. use the gs150 3 with gennum?s gs1545 or gs1522 for two chip hd sdi receive or transmit solutions. the GS1503 operates from a single 3.3v power supply with 5v tolerant i/o and is packaged in a 144 pin lqfp package. multiplex mode block diagram ordering information part number package temperature GS1503-cfz 144 pin lqfp 0c to 70c vin[19:0] 20 video detection & synchronization 20 vout[19:0] anci timing generation 4 video_det operate error crc_err de-scrambler & word alignment 20 crc inserter & scrambler trs inserter 20 dscbypass scrbypass host interface audio input interface ain1/2 ain3/4 ain5/6 ain7/8 cpuadr[8:0] cpudat[7:0] 4 9 8 2 wcina/b 3 arbitrary packet mux audio packet mux control packet mux host interface host interface 8 pkt[7:0] pkten pkteno 4 vm[3:0] mute am[1:0] 20 extf exth 2 cpucs, cpuwe, cpure GS1503 hd embedded audio codec
15879 - 4 2 of 83 GS1503 demultiplex mode block diagram absolute maximum ratings parameter value supply voltage -0.3v to 4.0v input voltage (any input) -0.3 to 5.5v operating temperature 0c to 70c storage temperature -65c to 150c lead temperature (soldering, 10 sec.) 230c dc electrical characteristics t a = 0c to 70c unless otherwise shown. parameter symbol conditions min typ max units supply voltage v dd 3.3v operating range 3.0 3.3 3.6 v supply current i dd v dd = 3.3v 270 ma input current i in -1 - 1 a hi-z output leakage current i oz -1 - 1 a output voltage, logic high v oh i oh = -12ma v dd -0.4 - - v output voltage, logic low v ol i ol = 12ma - - 0.4 v input voltage, logic high v ih ttl level 2.0 - - v input voltage, logic low v il ttl level - - 0.8 v input capacitance c i f = 1mhz, v dd = 0v - - 10 pf output capacitance c o f = 1mhz, v dd = 0v - - 10 pf i/o capacitance c io f = 1mhz, v dd = 0v - - 10 pf vin[19:0] 20 video detection & synchronization 20 vout[19:0] delete anci anci anci timing generation 4 video_det operate error crc_err mute de-scrambler & word alignment 20 crc inserter & scrambler 20 dscbypass scrbypass host interface cpuadr[8:0] cpudat[7:0] 9 8 3 pkt[7:0] arbitrary packet demux audio output interface 4 8 aout1/2 aout3/4 aout5/6 aout7/8 2 wcouta/b pkten audio packet demux control packet demux host interface host interface 4 vm[3:0] am[1:0] 2 cpucs, cpuwe, cpure
15879 - 4 3 of 83 GS1503 fig. 1 video data input setup & hold time ac electrical characteristics v dd = 3.3v 5%, t a = 0c to 70c unless otherwise shown. parameter symbol conditions min typ max units video clock frequency - 74.25 80 mhz video clock pulse width low t vpwl 5.0 - - ns video clock pulse width high t vpwh 5.0 - - ns video input data setup time t vs 3.5 - - ns video input data hold time t vh 1.0 - - ns video output data delay time t vod with 10pf loading - - 8.5 ns video output data hold time t voh with 10pf loading 1.0 - - ns audio clock frequency - 6.144 - mhz audio clock pulse width low t apwl 60 - - ns audio clock pulse width high t apwh 60 - - ns audio input data setup time t as 10.5 - - ns audio input data hold time t ah 1.0 - - ns audio output data delay time t aod with 10pf loading - - 20.0 ns audio output data hold time t aoh with 10pf loading 1.0 - - ns reset pulse width t reset 1- - ms device latency multiplexer mode demultiplexer mode 53 53 53 53 53 53 pclks vclk data* * vin[19:0], extf, exth, pkten, pkt[7:0] t vs t vh
15879 - 4 4 of 83 GS1503 fig. 2 video data output delay & hold time fig. 3 audio data input setup & hold time fig. 4 audio data output delay & hold time fig. 5 reset timing vclk data* * vout[19:0], extf, exth, pkten, pkt[7:0] t voh t vod aclka/b data* * wcina, ain1/2, ain3/4, wcinb, ain5/6, ain7/8 t as t ah aclka/b data* * aout1/2, aout3/4, aout5/6, aout7/8 t aoh t aod vdd reset t reset vdd(min) t reset
15879 - 4 5 of 83 GS1503 host interface fig. 6 host interface mode a timing (cpu_sel set high) mode a (cpu_sel set high) parameter number min typ max units read cycle time 1 50 - - ns read chip select setup time 2 0 - - ns read address setup time 3 15 - - ns read data output delay time 4 - - 15 ns read data hold time 5 0 - - ns write cycle time 6 50 - - ns write chip select setup time 7 10 - - ns write address setup time 8 10 - - ns write data setup time 9 10 - - ns write data hold time 10 0 - - ns cpuadr[8:0] cpudat[7:0] cpucs cpure valid data valid data 1 3 45 cpuwe address address 2 6 7 8 910 read cycle write cycle
15879 - 4 6 of 83 GS1503 fig. 7 host interface mode b read cycle timing (cpu_sel set low) mode b read cycle (cpu_sel set low) parameter number min typ max units read address cycle time 1 80 - - ns read cycle time 2 80 - - ns read enable setup time 3 20 - - ns read address setup time 4 20 - - ns read chip select setup time 5 10 - - ns read chip select hold time 6 0 - - ns read data output delay time 7 - - 10 ns read data hold time 8 0 - - ns cpuadr[1:0] cpudat[7:0] cpucs cpuwe 01 00 11 upper address lower address read data 112 3 4 5 3 4 5 666 3 5 7 8
15879 - 4 7 of 83 GS1503 fig. 8 host interface mode b write cycle timing (cpu_sel set low) mode b write cycle (cpu_sel set low) parameter number min typ max units write address cycle time 1 80 - - ns write cycle time 2 80 - - ns write enable setup time 3 20 - - ns write address setup time 4 20 - - ns write chip select setup time 5 10 - - ns write chip select hold time 6 0 - - ns write data setup time 7 30 - - ns write data hold time 8 0 - - ns cpuadr[1:0] cpudat[7:0] cpucs cpuwe 01 00 10 upper address lower address write data 112 3 4 5 3 4 5 666 3 5 7 8 table 1: host interface mode b control codes cpuadr[1:0] data bus operation 01 upper address 00 lower address 11 read data 10 write data
15879 - 4 8 of 83 GS1503 pin connections GS1503 top view 40 39 38 37 69 60 61 62 63 64 65 66 68 59 42 41 43 44 45 46 48 49 51 52 53 54 55 56 58 70 71 72 47 50 57 67 scrbypass rsv rsv rsv rsv exth extf video_det vout0 vout1 vout6 vout7 gnd vout8 vout9 vout10 vdd vout2 gnd vout11 vout12 vout13 gnd vout14 vout15 vdd vout16 vdd vout3 vdd vout4 vout5 vout17 vout18 vout19 gnd 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 122 121 120 119 118 117 116 115 114 113 112 111 110 109 138 139 140 141 142 143 144 vin19 vdd vin18 vin17 gnd vin16 vin15 vin14 vdd vin13 vin12 vin11 gnd vin10 vin9 vin8 vdd vin7 vin6 vin5 gnd vin4 vin3 vin2 vdd vin1 vin0 cpu_sel am1 am0 vm3 vm2 vm1 vm0 reset gnd 99 100 101 102 103 104 105 107 108 98 84 85 86 87 89 91 92 94 95 96 83 73 74 75 76 77 78 79 80 81 82 88 90 93 97 106 cpudat6 vdd wcouta wcoutb aout1/2 aout3/4 aout5/6 aout7/8 gnd cpuadr8 cpuadr7 cpuadr6 vdd dec_mode gnd vclk gnd cpuadr5 cpuadr0 cpuadr2 cpuadr3 cpudat0 cpudat1 vdd cpudat2 cpuadr4 cpudat3 cpudat4 cpudat5 vdd cpucs cpudat7 cpuwe gnd cpure 9 8 7 6 5 4 3 2 10 27 26 24 25 28 23 22 21 20 19 18 17 16 15 14 13 12 11 36 35 34 33 32 31 30 29 1 vdd ain1/2 wcinb wcina dscbypass pllcntb pllcnta anci vdd gnd aclka gnd cascade mute operate crc_error pkteno pkten pkt7 vdd pkt6 pkt5 pkt4 vdd pkt3 pkt2 pkt1 pkt0 gnd error gnd aclkb mux/demux ain3/4 ain5/6 ain7/8 cpuadr1
15879 - 4 9 of 83 GS1503 pin descriptions number symbol type description 1, 14, 27, 31, 37, 52, 60, 68, 73, 84, 97, 104, 109, 117, 125, 133 vdd - +3.3v power supply pins. 2 ain7/8 i audio signal input for channels 7 and 8. aes/ebu digital audio da ta is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 3 ain5/6 i audio signal input for channels 5 and 6. aes/ebu digital audio da ta is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 4 ain3/4 i audio signal input for channels 3 and 4. aes/ebu digital audio da ta is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 5 ain1/2 i audio signal input for channels 1 and 2. aes/ebu digital audio da ta is bi-phase mark encoded. for all non-aes/ebu input modes, bi-phase mark encoding is not required. 6 wcinb i 48khz word clock for channels 5 to 8. us ed only when operating in multiplex mode and when the audio source is not an aes/ebu data stream. this pin should be grounded when inputting aes/ebu digital audio data or when operating in demultiplex mode (dec_mode set low). 7 wcina i 48khz word clock for channels 1 to 4. us ed only when operating in multiplex mode and when the audio source is not an aes/ebu data stream. this pin should be grounded when inputting aes/ebu digital audio data or when operating in demultiplex mode (dec_mode set low). 8 dscbypass i descrambler bypass. when set low, the internal smpte 292m descrambler is enabled. when set high, the internal smpte 292m descrambler is bypassed. the video input to the device must be word aligned. 9 pllcntb o audio clock pll control signal for channels 5 to 8. 10 pllcnta o audio clock pll control signal for channels 1 to 4. 11 cascade i cascade mode select. when set high, the GS1503 will default to audio groups 3 and 4. two GS1503 devices can then be cascaded in se ries to allow up to 16 channels of audio to be multiplexed or demultiplexed (only one device requires cascade to be set high). when set low, the GS1503 will default to audio groups 1 and 2. 12 mute i audio mute. in multiplex mode, when set high, the embedded audio packets are forced to '0'. in demultiplex mode, when set high, the audio output data is forced to "0". 13 anci i ancillary data delete select. valid in de multiplex mode only. when set high, all ancillary data packets are removed from both the luma and chroma channels of the input video signal. the data contained in the packets are output at the corresponding pins. when set low, all ancillary data packets remain in the video signal. see section 2-11. 15 mux /demux i mode of operation. when set low, the GS1503 operates in multiplex mode. when set high, the GS1503 operates in demultiplex mode. 16, 18, 20, 36, 48, 56, 64, 72, 80, 86, 88, 108, 113, 121, 129, 144 gnd - device ground. 17 aclka i input audio signal clock at 6.144 mhz (128 fs) for channels 1 to 4. 19 aclkb i input audio signal clock at 6.144 mhz (128 fs) for channels 5 to 8. 21 error o format error indicator. when high, the inco ming video data stream contains trs errors or there are errors within the incoming ancillary data packets.
15879 - 4 10 of 83 GS1503 22 operate o audio processing indicator. when hi gh, audio data is being multiplexed or demultiplexed. 23 crc_error o crc error indicator. will be set high when a crc error is detected in the incoming video data stream. 24 pkteno o arbitrary data packet timing signal. va lid in multiplex mode only. will be high when arbitrary data packets can be input to t he device. this signal is only valid when multiplexing arbitrary data p ackets via the pkt[7:0] bus. see figure 30 for timing. 25 pkten i/o arbitrary data packet enable. in multiplex mode, pkten is an input and must be set high two vclk cycles after the pkteno signal goes high. arbitrary packet data is input to the device two vclk cycles after pkten is set high. in demultiplex mode, pkten is an output and is set high two vclk cycles before the device outputs arbitrary packet data. see figures 30 and 42. 26, 28, 29, 30, 32, 33, 34, 35 pkt[7:0] i/o arbitrary data i/o bus. pkt[7] is the ms b and pkt[0] is the lsb. in multiplex mode, the user must input the arbitrary data packet word s starting from the data identification (did) to the last user data word (udw) according to smpte 291m. the GS1503 internally converts the data to 10 bits by generating the pa rity bit (bit 8) and inversion bit (bit 9). the checksum (cs) word is also generated internally. in demultiplex mode, the gs9023 outputs the arbitrary data packet words starting from the did to the last udw. see figures 30 and 42. 38 scrbypass i scrambler bypass. when set low, the output video stream is scrambled according to smpte 292m and nrz(i) encoded. when set high, the scrambler and nrz(i) encoder are bypassed. 39, 40, 41, 42 rsv - connect to ground. 43 exth i/o horizontal sync signal. the GS1503 outputs a horizontal sync sig nal derived from the incoming trs. in multiplex mode, with ext_sel set high in the host interface, a horizontal sync signal can be input to the device for trs and line number insertion. 44 extf i/o field sync signal. the gs 1503 outputs a field sync signal derived from the incoming trs. in multiplex mode, with ext_sel set high in the host interface, a field sync signal can be input to the device for trs and line number in sertion. for progressive formats, a signal with a high to low transition at the posi tion of line one must be provided. see figures 14 and 15. 45 video_det o video input signal detection. indicates that the device has detected a valid video input stream. note: when ext_sel is set high in the ho st interface, video_det will indicate when valid exth and extf signals have been detected. 71, 70, 69, 67, 66, 65, 63, 62, 61, 59, 58, 57, 55, 54, 53, 51, 50, 49, 47, 46 vout[19:0] o parallel digital video signal output. vout[19] is the msb and vout[0] is the lsb. 74 wcouta o 48khz word clock for channels 1 to 4. va lid only when operating in demultiplex mode. 75 wcoutb o 48khz word clock for channels 5 to 8. va lid only when operating in demultiplex mode. 76 aout1/2 o audio signal output for channels 1 and 2. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. 77 aout3/4 o audio signal output for channels 3 and 4. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. 78 aout5/6 o audio signal output for channels 5 and 6. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. pin descriptions (continued) number symbol type description
15879 - 4 11 of 83 GS1503 79 aout7/8 o audio signal output for channels 7 and 8. the aes/ebu digital audio output is bi-phase mark encoded. in both non-aes/ebu modes, the output is not bi-phase mark encoded. 85 dec_mode i demultiplex mode select. valid in demultiplex mode only. when set high, the GS1503 requires a 48khz word clock input at wc ina and wcinb. this word clock must be synchronous to the word clock used to embed the audio data. the embedded audio clock phase information in the ancill ary data packet will be ignored. see section 2-11. 87 vclk i video clock signal input. 81, 82, 83, 89, 94, 93, 92, 91, 90 cpuadr[8:0] i host interface address bus. cpuadr[8] is the msb and cpuadr[0] is the lsb. in host interface mode b (cpu_sel set low), cpuadr[1:0] are used as the host interface control bus. see table 1. 103, 102, 101, 100, 99, 98, 96, 95 cpudat[7:0] i/o host interface data bus. cpudat[7] is the msb and cpudat[0] is the lsb. in host interface mode b (cpu_sel set low), cpudat[7:0] are used as the host interface address and data bus. 105 cpucs i chip select for host interface. active low. 106 cpure i read enable for host interface. active low. in host interface mode b (cpu_sel set low), this input is not used. 107 cpuwe i write enable for host interface. active low. in host interface mode b (cpu_sel set low), this input is used as the host interface control enable. 110, 111, 112, 114, 115, 116, 118, 119, 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135 vin[19:0] i parallel digital vid eo signal input. vin[19] is t he msb and vin[0] is the lsb. 136 cpu_sel i host interface mode select. when set high, the GS1503 is configured for host interface mode a. when set low, the GS1503 is configured for host interface mode b. 137, 138 am[1:0] i audio format select. in multiplex mode, am[1:0] indicates the input audio data format. in demultiplex mode, am[1:0] indicates the output audio data format. am[1] is the msb and am[0] is the lsb. see tables 3 and 11. 139, 140, 141, 142 vm[3:0] i video standard select. vm[3] is the msb and vm[0] is the lsb. see table 2 or 10. 143 reset i device reset. active low. pin descriptions (continued) number symbol type description
15879 - 4 12 of 83 GS1503 detailed description 1. multiplex mode 1.1 functional overview the GS1503 hd embedded audio codec fully supports the multiplexing of audio da ta packets, audio control packets and arbitrary data packets as per smpte 291m and 299m. the device can be co nfigured to operate with all video standards defined in sm pte 292m, levels a through m. the GS1503 also supports the 1080/24psf, 25psf and 30psf video formats as described in smpte rp211. the video input format can be one of the following configurations: 10-bit y and c b /c r input with trs and line numbers 8-bit y and c b /c r input with trs and line numbers 10-bit or 8-bit y and c b /c r input without trs and line numbers (GS1503 will insert trs and line numbers based on extf and exth inputs) 20-bit scrambled input the video output format can be one of the following configurations: 20-bit scrambled output 10-bit y and c b /c r output up to a maximum of 8 channels of 48khz digital audio can be multiplexed per device. the audio input format can be selected as either aes/ebu, or one of two serial audio data input modes. a maximum of 16 channels of audio can be multiplexed by serially cascading two devices. audio control packets, as defined in smpte 299m, can also be multiplexed to provide info rmation to receivers about the nature of the embedded audio data. the contents of the audio control packet can be programmed via the host interface. the GS1503 will also multiplex arbitrary data packets as defined in smpte 291m. the arbitrary data packets can serve as an auxiliary data signal for proprietary applications. the GS1503 can be configured to multiplex arbitrary data packets, input via the host interface or using dedicated external pins. up to a maximum of 255 8-bit words can be multiplexed (excluding ancillary data flags and checksum). to use the GS1503 in multiplex mode, set the mux /demux external pin low. 1.2 video standard the video standard is selected from the vm[3:0] external pins or vm[3:0] bits 3-0 in host interface register 000h. to configure the video standard via the host interface, vm_sel bit 7 in host interface register 000h must be set high. the GS1503 will default to the vm[3:0] external pin setting. the supported video standards are listed in table 2. table 2: supported video standards vm [3:0] input format reference smpte document smpte 292m level 1110b 1035i (30 & 30/1.001 hz) 260m a, b 1100b 1080i (25 hz) 295m c 1000b 1080i/1080sf (30 & 30/1.001 hz) 274m, rp211 d, e 1010b 1080i/1080sf (25 hz) 274m, rp211 f 1111b 1080sf (24 & 24/1.001 hz) rp211 0010b 1080p (30 & 30/1.001 hz) 274m g, h 0100b 1080p (25 hz) 274m i 0110b 1080p (24 & 24/1.001 hz) 274m j, k 0000b 720p (60 & 60/1.001 hz) 296m l, m 0001b 720p (30 & 30/1.001 hz) 296m 0011b 720p (50 hz) 296m 0101b 720p (25 hz) 296m 0111b 720p (24 & 24/1.001 hz) 296m all other settings are reserved
15879 - 4 13 of 83 GS1503 1.3 video input format 1.3.1 10-bit y and c b /c r input video with trs and line numbers fig. 9 configuration for 10-bit y and c b /c r input video with trs and line numbers fig. 10 video input format 10-bit with trs and line numbers register settings name description address bit setting default vm_sel 0: external pin select 1: register select 000 7 1 0 vm[3:0] video formal selection (vm[3] is msb) 3-0 see ta b l e 2 0 y[9:0] c b /c r [9:0] vin[19:10] vin[9:0] dscbypass extf exth GS1503 +3.3v vn y, c b /c r 3ff 3ff xyz 000 000 000 000 xyz 10-bit ln1 ln0 crc0 crc1 v0 video eav sav 0 3 8 register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 01 0
15879 - 4 14 of 83 GS1503 1.3.2 8-bit y and c b /c r input video with trs and line numbers fig. 11 configuration for 8-bit y and c b /c r input video with trs and line numbers fig. 12 video input format 8-bit with trs and line numbers y[9:0] c b /c r [9:0] vin[19:12] vin[9:2] dscbypass extf exth GS1503 vin[1:0] vin[11:10] +3.3v vn y, c b /c r ff ff xy 00 00 00 00 xy 8-bit ln1 ln0 v0 video eav sav 0 3 8 register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 11 0 dscbypass 0: descrambling enabled 1: bypass descrambling 01 0
15879 - 4 15 of 83 GS1503 1.3.3 10-bit or 8-bit y and c b /c r input without trs and line numbers the GS1503 will insert trs and line numbers based on extf and exth inputs. see figure 14 for timing. in progressive format video st andards, a high-to-low edge signal must be input at the extf external pin on every frame to indicate the position of line 1. see figure 15. fig. 13 configuration for 10-bit or 8-bit y and c b /c r input video without trs and line numbers fig. 14 video input format (8/10-bit without trs and line numbers) fig. 15 video input format (progressive) y[9:0] c b /c r [9:0] vin[19:10] vin[9:0] dscbypass extf exth GS1503 +3.3v vn y, c b /c r 8/10-bit v0 video 0 3 8 4 vclk exth extf vn y, c b /c r 8/10-bit v0 video 0 3 8 4 vclk exth extf line 1
15879 - 4 16 of 83 GS1503 1.3.4 20-bit scrambled input fig. 16 configuration for 20-bit scrambled input register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 1 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 10 or 1 0 dscbypass 0: descrambling enabled 1: bypass descrambling 01 0 register settings (default mode) name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 00 0 y/c b /c r [19:0] vin[19:0] dscbypass GS1503
15879 - 4 17 of 83 GS1503 1.4 video output format 1.4.1 20-bit scrambled output fig. 17 configuration for 20-bit scrambled output 1.4.2 10-bit y and c b /c r output fig. 18 configuration for 10-bit y and c b /c r output register settings (default mode) name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 0 0 y/c b /c r [19:0] vout[19:0] scrbypass GS1503 register settings name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 1 0 y[9:0] c b /c r [9:0] vout[19:10] vout[9:0] scrbypass GS1503 +3.3v
15879 - 4 18 of 83 GS1503 1.5 video data processing 1.5.1 video signal input detection the GS1503 will set the video_det external pin high when three consecutive trs are detected in the input video signal. also, the video_det bi t of host interface register 000h is set high. 1.5.2 video input crc error detection the GS1503 will set the crc_err external pin high when a crc error is detected in the input video signal. also, the crc_err bit 5 of host interface register 000h is set high. the number of crc errors accumulated in one video frame can be read form crc_cnt[11:0] in host interface registers 006h and 007h. 1.5.3 video output crc insertion when the crc_ins bit 4 of host interface register 000h is set high, the GS1503 will re-calculate the video line crc words. the re-calculated crc words are inserted in the video output signal. when crc_ins is set low, the line crc words are not updated and existing crc words at the input of the device will be output unchanged. register settings name description address bit setting default video_det video input signal detection (1: detection) 000 6 - 0 register settings name description address bit setting default crc_err video input signal crc erro r detection (1: detection) 000 5 - 0 crc_cnt[11:0] video input signal crc error accumulation in 1 video frame 006 007 3-0 7-0 -0 register settings name description address bit setting default crc_ins video line crc insertion (1: insertion) 000 4 1 1
15879 - 4 19 of 83 GS1503 1.5.4 illegal code re-mapping when limit_on bit 4 of host interface register 008h is set high, input video words between 000-003 are re-mapped to 004, and values between 3fc-3ff are re-mapped to 3fb. valid only when the ext_ sel bit 3 of host interface register 000h is set high. 1.5.5 input blanking when vblk_ins bit 3 of host interface register 008h is set high, the input video vertical bl anking will be set to 040h for the luma channel and 200h for the chroma channel. when hblk_ins bit 2 of host interface register 008h is set high, the input video horizontal blanking will be set to 040h for the luma channel and 200h for the chroma channel. the trs, line number and crc words will also be set to blanking values. the blanking function is perf ormed at the output of the GS1503 video data stream. if th e hblk_ins bit is set high, any multiplexed audio will be replaced with blanking codes. 1.5.6 line number insertion when ln_ins bit 1 of host interface register 008h is set high, the GS1503 will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. when ext_sel bit 3 of host in terface register 001h is set high, line numbers will be inserted based on the timing of exth and extf input signals. register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 1 0 limit_on illegal code re-mapping (1: enabled) 008 4 1 0 register settings name description address bit setting default vblk_ins input vertical blanking (1: enabled) 008 3 1 0 hblk_ins input horizontal blanking (1: enabled) 2 1 0 register settings name description address bit setting default ln_ins line number insertion (1: enabled) 008 1 1 1
15879 - 4 20 of 83 GS1503 1.5.7 trs word insertion when trs_ins bit 0 of host interface register 008h is set high, the GS1503 will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. when ext_sel bit 3 of host in terface register 001h is set high, trs codes will be inserted based on the timing of exth and extf input signals. 1.6 audio data processing 1.6.1 digital audio input format the GS1503 will accept two audio input formats, aes/ebu digital audio input and serial input, as listed in table 3. serial input can be formatted in the following two modes. see figure 19: 24-bit left justified; msb first 24-bit right just ified; msb last the audio input format is configured using the am[1:0] external pins or via am[1:0] bits 1-0 in host interface register 010h. to configure t he audio input format via the host interface, am_sel bit 7 in host interface register 010h must be set high. the GS1503 will default to the am[1:0] external pin setting. fig. 19 audio input formats register settings name description address bit setting default trs_ins trs word insertion (1: enabled) 008 0 1 1 table 3: audio input formats am[1:0] audio input format 0 serial audio input: 24-bit left justified; msb first 1 serial audio input: 24-bit right justified; msb last 2 aes/ebu audio input register settings name description address bit setting default am_sel 0: external pin setting 1: register setting 010 7 1 0 am[1:0] audio input format selection (am[1] is msb) 1-0 see ta b l e 3 0 23 channel 1 msb channel 2 wcina/wcinb 0 0 lsb 23 23 msb 0 0 lsb 23 mode1 mode0 mode2 (aes/ebu) sync preamble 24-bit audio sample word vucp 0 3 4 2728293031 channel status bit validity bit user data bit parity bit sync preamble 24-bit audio sample word vucp 0 3 4 2728293031
15879 - 4 21 of 83 GS1503 1.6.2 digital audio input timing 1.6.2.1 aes/ebu format input a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. acl ka is used to clock the aes/ebu digital audio signal for channels 1 to 4 (ain1/2 and ain3/4) into the device. aclkb is used to clock the aes/ebu digital audio signal for channels 5 to 8 (ain5/6 and ain7/8) into the device. in aes/ebu input mode, the wcinb and wcinb external pins should be grounded. see figure 20 for timing. fig. 20 aes/ebu input configuration and timing aclka/b ain1/2, ain3/4 ain5/6, ain7/8 6.144mhz y/c b /c r [19:0] vin[19:0] ain5/6 GS1503 ain1/2 ain3/4 ain7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) wcina wcinb
15879 - 4 22 of 83 GS1503 1.6.2.2 serial audio input modes a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. the GS1503 divides this clock by 2 to clock the 3.072mhz audio data. an audio word clock at 48khz (fs) must also be supplied to the wcina and wcinb inputs, as shown in figure 21. the audio_cs[183:0] bits in host interface registers 058h to 06eh can be used to enter t he 23 8-bit bytes of the audio channel status block, as defi ned in aes3-1992. note: the crc byte is generated internally by the GS1503. the GS1503 will default to professional audio mode with 24-bit word length and emphasis off. see table 9 . fig. 21 serial audio input configuration and timing y/c b /c r [19:0] vin[19:0] ain5/6 GS1503 ain1/2 ain3/4 ain7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) aclka/b ain1/2, ain3/4 ain5/6, ain7/8 64 clks 48khz (fs) 48khz (fs) wcina wcinb wcina/b 64 clks
15879 - 4 23 of 83 GS1503 1.6.3 audio clock phase locked loop figure 22 shows the configuration for deriving the 6.144mhz audio clock in aes/ebu audio input mode. the GS1503 will internally synchroni ze the aes/ebu audio input to the corresponding aclk, using the clock extracted from the aes/ebu bi-phase mark encoding. this configuration is not required for serial audio input modes. see the reference design section 3 for circuit specifics . fig. 22 block diagram of GS1503 audio clock pll 1.6.4 audio signal input detection the audio input signal detect registers will be set high in aes/ebu audio mode when the preamble of the audio input data is detected 3 times consecutively. in serial audio input mode, the GS1503 will set the audio input signal detect registers high when a 48khz wo rd clock is detected at the corresponding inputs. audio channels 1 to 4 will be set when wcina is validated, and audio channels 5 to 8 when wcinb is validated. host interf ace register 010h, bits 6-3, report the individual audio channels pairs detected. y/c b /c r [19:0] vin[19:0] ain5/6 GS1503 ain1/2 ain3/4 ain7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) pllcnta pllcntb low pass filter vcxo 24.576mhz vcxo 24.576mhz 4 4 6.144mhz (128 fs) low pass filter register settings name description address bit setting default aud7/8_det ch7/8 audio input signal detection (1:detection) 010 6 - 0 aud5/6_det ch5/6 audio input signal detection (1:detection) 5 - 0 aud3/4_det ch3/4 audio input signal detection (1:detection) 4 - 0 aud1/2_det ch1/2 audio input signal detection (1:detection) 3 - 0
15879 - 4 24 of 83 GS1503 1.6.5 audio channel status crc error detection in aes/ebu audio mode, the GS1503 will check the channel status crc for errors. if any channel status crc errors are detected in an ae s/ebu audio input channel pair, the corresponding bit in host interface register 011h will be set high. in serial audio in put mode, the crc error flags are always set low. 1.6.6 audio input parity error detection in aes/ebu audio mode, the GS1503 will check for audio parity errors. if any audio parity errors are detected in an aes/ebu audio input channel pair, the corresponding bit in host interface register 012h will be set high. in serial audio input mode, the audi o parity error flags are always set low. 1.6.7 audio channel status crc insert function when bits 7-4 of host interf ace register 011h are set high, the GS1503 will re-calculate the channel status crc word for the corresponding audio input channel pair. the re- calculated channel status crc word is multiplexed into the audio data packet as per smpte 299m. when bits 3-0 of host interface register 011h are set low, the channel status crc word is not upda ted and the existing channel status crc word will be multiplexed. in serial audio input mode, these registers should be set low. register settings name description address bit setting default acrc7/8_err ch7/8 audio channel status crc error detection (1: detection) 011 3 - 0 acrc5/6_err ch5/6 audio channel status crc error detection (1: detection) 2- 0 acrc3/4_err ch3/4 audio channel status crc error detection (1: detection) 1- 0 acrc1/2_err ch1/2 audio channel status crc error detection (1: detection) 0- 0 register settings name description address bit setting default ap7/8_err ch7/8 audio parity error detection (1: detection) 012 3 - 0 ap5/6_err ch5/6 audio parity error detection (1: detection) 2 - 0 ap3/4_err ch3/4 audio parity error detection (1: detection) 1 - 0 ap1/2_err ch1/2 audio parity error detection (1: detection) 0 - 0 register settings name description address bit setting default acrc7/8_ins ch7/8 audio channel status crc insertion (1: insertion) 011 7 1 0 acrc5/6_ins ch5/6 audio channel status crc insertion (1: insertion) 6 1 0 acrc3/4_ins ch3/4 audio channel status crc insertion (1: insertion) 5 1 0 acrc1/2_ins ch1/2 audio channel status crc insertion (1: insertion) 4 1 0
15879 - 4 25 of 83 GS1503 1.7 audio data packets 1.7.1 audio data packet structure figure 23 shows the structure of the audio data packets as defined in smpte 299m. the audio data packets are multiplexed into the chroma channel of the video data stream. table 4 lists the description of the individual audio data packet words. note that the GS1503 will automatically generate certain audio data packet words. fig. 23 audio data packet structure 1.7.2 audio data packet did setting the audio group did for audio input channels 1 to 4 (ain1/ 2 and ain3/4) is set in dataida[1:0] bits 1-0 of host interface register 014h. the audio group did for audio input channels 5 to 8 (ain5/6 and ain7/8) is set in dataidb[1:0] bits 3-2 of host interface register 014h. table 5 shows the 2-bit host interface setting for the corresponding audio group did. when cascade is set low (external pin or register), the GS1503 will default to audio groups 1 and 2, where ain1/2 and ain3/4 will be multiplexed with audio group 1 did, and ain5/6 and ain7/8 with audio group 2 did. table 4: audio data packet word descriptions name no of words description data auto-generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 2e7h 1e6h 1e5h 2e4h see table 5 in section 1-7-2 dbn 1 data block number repeat 1-255 yes dc 1 data count 218h yes clk 2 audio clock phase data - yes ch1 4 channel 1 audio data - ch2 4 channel 2 audio data - ch3 4 channel 3 audio data - ch4 4 channel 4 audio data - ecc0-5 6 error correction code for lower 8 bits of first 24 words - yes cs 1 checksum. calculates the sum of lower 9 bits of 22 words from did -yes adf user data words ecc0 10-bit did dbn dc clk ch1 ch2 ch3 ch4 ecc1 ecc2 ecc3 ecc4 ecc5 cs ecc protected
15879 - 4 26 of 83 GS1503 when cascade is set high (external pin or register), the GS1503 will default to audio groups 3 and 4, where ain1/2 and ain3/4 will be multiplexed with audio group 3 did, and ain5/6 and ain7/8 with audio group 4 did. 1.7.3 audio channel multiplex enable multiplexing of individual aud io channels is enabled using the chact[7:0] bits 7-0 of host interface register 013h. when set high, the corresponding audio channel is multiplexed into the audio data packet in the chroma video data stream. chact7 corresponds to audio input channel 8 and chact0 corresponds to audio input channel 1. when all bits are set low, no audio data packets will be multiplexed and the GS1503 will be in bypass mode. table 5: audio data packet group did host interface setting audio group 10-bit data host interface register setting (2-bit) 1 2e7h 11b 2 1e6h 10b 3 1e5h 01b 4 2e4h 00b register settings (cascade set low) name description address bit setting default dataida [1-0] ch1-4 audio data packet did setting 014 1-0 see ta b l e 5 11b dataidb [1-0] ch5-8 audio data packet did setting 3-2 10b register settings (cascade set high) name description address bit setting default dataida [1-0] ch1-4 audio data packet did setting 014 1-0 see ta b l e 5 01b dataidb [1-0] ch5-8 audio data packet did setting 3-2 00b register settings name description address bit setting default chact7 ch8 multiplex enable (1: enabled) 013 7 - 1 chact6 ch7 multiplex enable (1: enabled) 6 1 chact5 ch6 multiplex enable (1: enabled) 5 1 chact4 ch5 multiplex enable (1: enabled) 4 1 chact3 ch4 multiplex enable (1: enabled) 3 1 chact2 ch3 multiplex enable (1: enabled) 2 1 chact1 ch2 multiplex enable (1: enabled) 1 1 chact0 ch1 multiplex enable (1: enabled) 0 1
15879 - 4 27 of 83 GS1503 1.8 video switching line setting the video switching point for field 1 and field 2 can be configured via the GS1503 host interface. the sw_lna[12:0] register is used to configure the video switching line for field 1, and sw_lnb[12:0] to set video switching line for field 2. in progressive format video standards, only the sw_lna[ 12:0] register is used. the default settings are line 7 for field 1 and line 569 for field 2 as defined in smpte 299m. the GS1503 will not multiplex an y audio data packets in the line immediately after the video switching point. for example, with the default setting of line 7 field 1, there will be no audio data packets in line 8. the next packets will appear on line 9. audio control packets will be multiplexed once per field, two lines after the video switching point (on line 9, using the previous example). arbitrary data packets will not be multiplexed in the two lines following the video switching point . note: the smpte 299m standard defines the video switching point as lines 7 and 569. if the sw_lna[12:0] and sw_lnb[12:0] registers are programmed with values other than lines 7 and 569, the ou tput of the GS1503 is not guaranteed to be compatible with all hd audio demultiplex systems. with non-smpte 29 9m compliant switch line settings, the user should avoid inputting a video data stream to the GS1503, whic h already contains embedded audio data and control packets. for reliable operation, non- smpte 299m compliant video data streams with embedded aud io should not be used in conjunction with the GS1503 in multiplex mode. 1.9 multiplex cascade mode two GS1503 devices can be cascaded in series to allow up to 16 channels of audio to be multiplexed (only one device requires cascade to be set high). figure 24 shows the cascade architecture for a 16-channel system. to configure the GS1503 for cascade mode, the cascade external pin or cascade bit 7 of host interface register 014h is set high. when set high, the GS1503 will default to audio groups 3 and 4. when set low, the GS1503 will default to audio groups 1 and 2. fig. 24 multiplexing 16 channels of audio using cascade architecture register settings name description address bit setting default sw_lna[12:0] video field 1 switching point setting 004 005 4-0 7-0 -7d sw_lnb[12:0] video field 2 switching point setting 002 003 4-0 7-0 -569d register settings name description address bit setting default cascade cascade enable (1: enabled) 014 7 1 0 y/c b /c r [19:0] vin[19:0] ain5/6 GS1503 ain7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 cascade vout[19:0] audio group 1 audio group 2 ain1/2 ain3/4 y/c b /c r [19:0] vin[19:0] ain5/6 GS1503 ain7/8 audio channels 9 & 10 audio channels 11 & 12 audio channels 13 & 14 audio channels 15 & 16 cascade vout[19:0] audio group 3 audio group 4 ain1/2 ain3/4 y/c b /c r [19:0] +3.3v
15879 - 4 28 of 83 GS1503 when cascade is set low, the GS1503 will multiplex audio data and control pack ets as shown in figure 25 (note: only the chroma channel of the video data stream is shown). any existing audio data or control packets will be deleted and replaced with blanking data before the new packets are multiplexed. ne w packets are multiplexed immediately after the two video line crc words. when cascade is set high, the GS1503 will multiplex the audio data and control packets immediately after the existing packets, as shown in figure 26. avoid multiplexing new ancillary data packets with the same audio group did as existing packets. fig. 25 fig. 26 blank (200 h ) video signal before GS1503 (no existing audio data packets) sav blank (200 h ) eav video signal before GS1503 (with existing audio data packets) sav audio group 1 audio group 2 blank (200 h ) eav video signal after GS1503 insertion of audio groups 1 & 2 (cascade = 0) sav audio group 1 (new) audio group 2 (new) eav ln crc ln crc ln crc blank (200 h ) eav video signal before GS1503 (with existing audio data packets) sav audio group 1 audio group 2 blank (200 h ) eav video signal after GS1503 insertion of audio groups 3 & 4 (cascade = 1) sav audio group 1 (old) audio group 2 (old) audio group 3 (new) audio group 4 (new) ln crc ln crc
15879 - 4 29 of 83 GS1503 the GS1503 assumes that the ancillary data space from the first blanking location to the sav contains no ancillary data packets. existing ancillary data packets must be contiguous from the beginnin g of the hanc space or the GS1503 will overwrite existing packets with blanking before multiplexing new packets. see figure 27 . fig. 27 1.10 audio control packets 1.10.1 audio control packet structure figure 28 shows the structure of the audio control packet as defined in smpte 299m. an audio control packet is multiplexed once per field in the luma channel of the video data stream. table 6 lists descriptions of the individual audio control packet words. the GS1503 will automatically generate certain audio control packet words. fig. 28 audio control packet structure blank (200 h ) blank (200 h ) eav video signal before GS1503 (with space between eav and existing audio data packets) sav audio group 1 audio group 2 video signal after GS1503 insertion of audio groups 3 & 4 (cascade = 1) blank (200 h ) eav sav audio group 3 (new) audio group 4 (new) ln crc ln crc adf user data words 10-bit did dbn dc af del1-2 del3-4 rsrv cs rate act
15879 - 4 30 of 83 GS1503 1.10.2 audio control packet did setting to multiplex audio control packets for audio channels 1 to 4 (inputs ain1/2 and ain3/4), the ctrona bit 2 of host interface register 02fh must be set high. to multiplex audio control packets for audio channels 5 to 8 (inputs ain5/6 and ain7/8), the ctro nb bit 2 of host interface register 020h must be set high. the audio control packet gr oup did for audio input channels 1 to 4 is set in ctrida[1:0] bits 1-0 of host interface register 02fh. the au dio control packet group did for audio input channels 5 to 8 is set in ctridb[1:0] bits 3-2 of host interface register 020h. table 7 shows the 2-bit host interface setting for the corre sponding audio control packet group did. when cascade is set low (ext ernal pin or register), the GS1503 will default to audio groups 1 and 2, where the audio control packet for ain1/2 and ain3/4 will be multiplexed with group 1 did, and ain5/6 and ain7/8 with group 2 did. control packet data can be programmed via the corresponding registers in the host interface. table 6: audio control packet word descriptions name no of words description data auto- generation adf 3 ancillary data flag 000h 3ffh 3ffh yes did 1 audio group data id 1e3h 2e2h 2e1h 1e0h see table 7 in section 1-10-2 dbn 1 data block number 200h yes dc 1 data count 10bh yes af 1 audio frame number - 9-bit host interface setting rate 1 sampling frequency - 4-bit host interface setting act 1 active channel - chact[7:0] setting del1-2 3 ch1/2 delay data - 26-bit host interface setting del3-4 3 ch3/4 delay data - 26-bit host interface setting rsrv 2 reserved words 200h 18-bit host interface setting cs 1 checksum. calculates the sum of lower 9 bits of 15 words from did -yes table 7: audio control packet group did host interface settings audio group 10-bit data host interface register setting (2-bit) 1 1e3h 11b 2 2e2h 10b 3 2e1h 01b 4 1e0h 00b
15879 - 4 31 of 83 GS1503 register settings name description address bit setting default ctrona ch1-4 audio control packet multiplex enable (1: enabled) 02f 2 1 1 ctrida[1:0] ch1-4 audio control packet did set 1-0 see ta b l e 7 11b af_noa[8:0] ch1-4 audio frame number 030 031 0 7-0 0 ratea[2:0] ch1-4 sampling frequency data 032 3-1 - 0 asxa ch1-4 synchronization (0:synchronous; 1: non-synchronous) 0- 0 del1-2a[25:0] ch1/2 delay data 033 034 035 036 1-0 7-0 7-0 7-0 -0 del3-4a[25:0] ch3/4 delay data 037 038 039 03a 1-0 7-0 7-0 7-0 -0 rsrva[17:0] ch1-4 reserved words 03b 03c 03d 1-0 7-0 7-0 -0 ctronb ch5-8 audio control packet multiplex enable (1: enabled) 020 2 1 1 ctridb[1:0] ch5-8 audio control packet did set 1-0 see ta b l e 7 10b af_nob[8:0] ch5-8 audio frame number 021 022 0 7-0 -0 rateb[2:0] ch5-8 sampling frequency data 023 3-1 - 0 asxb ch5-8 synchronization (0:synchronous; 1: non-synchronous) 0- 0 del1-2b[25:0] ch5/6 delay data 024 025 026 027 1-0 7-0 7-0 7-0 -0 del3-4b[25:0] ch7/8 delay data 028 029 02a 02b 1-0 7-0 7-0 7-0 -0 rsrvb[17:0] ch5-8 reserved words 02c 02d 02e 1-0 7-0 7-0 -0
15879 - 4 32 of 83 GS1503 1.11 arbitrary data packets the GS1503 can multiplex arbitrary data packets according to smpte 291m. typically, this consists of linear time code (ltc), vertical interval time code (vitc) or other user data, which is multiplexed once per video field. the GS1503 has two modes in which arbitrary data can be multiplexed into the luma channel of the video data stream. a maximum of 255 user data words can be multiplexed in one packet. figure 29 shows the structure of the arbitrary data packet. note: arbitrary data packets will not be multiplexed in the two lines following the video switching point (see section 1.8). fig. 29 arbitrary data packet structure 1.11.1 arbitrary data multiplexing in external pin mode this is the default mode for multiplexing arbitrary data packets. the GS1503 will set the pkteno external pin high when arbitrary data can be input to the device. two vclk cycles after pkteno goes high, the user should set the pkten arbitrary packet enable pin high. two vclk cycles after pkten is set high, arbitrary data can be input at the pkt[7:0] bus. see figure 30 for timing. the user is required to enter the following arbitrary data: data id (did), secondary data id (sdid), data count (dc) and user data words (udw: maximum of 255), via the pkt[7-0] pins. this GS1503 automatically generates the ancillary data flag (adf), checksum (cs) and bit 8 (parity bit) and bit 9 (not bit 8). the pkteno pin will be set high on all video lines except the two lines following the video switching point. for example, with the default setting of line 7 field 1, pkteno will not be set high on lines 8 and 9. the switching point is set in the sw_lna[12:0] and sw_lnb[12:0] host interface registers for field 1 and field 2 respectively. see section 1-8. fig. 30 arbitrary data packet input timing diagram adf user data words msb did sdid dc udw0[100] cs contents set in host interface registers udw254[1fe] udw253[1fd] udw252[1fc] udw251[1fb] udw1[101] udw2[102] udw3[103] lsb not b8 parity bit y/c b /c r [19:0] vin[19:0] GS1503 pkteno pkten pkt[7:0] arbitrary data packet timing arbitrary data input enable arbitrary data vclk pkt[7:0] 2 clks 2 clks 2 clks 2 clks arbitrary data pkteno pkten automatically generated by the GS1503 udw254 udw253 udw252 udw251 udw250 cs udw3 udw2 udw1 udw0 dc sdid did adf adf adf arbitrary packet
15879 - 4 33 of 83 GS1503 1.11.2 arbitrary data multiplexing in host interface mode to select this mode, set arbitm ode bit 0 in host interface register 050h high. in this mode, the did, sdid, dc and user data words must be programmed via the corresponding host interface registers. set the video line number for field 1 and field 2 in which the arbitrary data packets are to be multiple xed using the arbitlinea[11:0] and arbitlineb[11:0] host interface registers respectively. the arbitrary data packet is multiplexed when arbiton bit 1 in host interface register 050h is set high. arbiton should be set low during the pr ogramming of the arbitrary data packet in the host interface. arbitlinea[11:0] an d arbitlineb[11:0] should not be set to the two line numbers following the line number set in the sw_lna[12:0] and sw_l nb[12:0] host interface registers. for example, with the default setting of line 7 field 1, arbitlinea[11:0] should not be set to line 8 or 9. register settings name description address bit setting default arbiton arbitrary packet multiplex enable (1: enabled) valid only when arbitmode is high 050 1 1 0 arbitmode arbitrary packet mode selection (0: external pin mode; 1: host mode) 01 0 arbitdid[7-0] arbitrary packet did setting 051 7-0 - 0 arbitsdid[7-0] arbitrary packet sdid setting 052 7-0 - 0 arbitdc[7-0] arbitrary packet dc setting 053 7-0 - 0 arbitlinea[11:0] field 1 multiplexing line 054 055 3-0 7-0 -0 arbitlineb[11:0] field 2 multiplexing line 056 057 3-0 7-0 -0 arbitudw arbitrary packet udw setting 100-1fe 7-0 - 0
15879 - 4 34 of 83 GS1503 table 8: multiplex mode host interface registers control item name description address bit r/w default video vm_sel video input format (external pin/internal register) configuration select. when set low, the video input format is configured via the vm[3:0] pins. when set high, the video input format is configured via the "vm[3:0]" bits. 000 7 r/w 0 video_det video signal detection flag. set high when 3 consecutive trs are detected in the input video signal. 6r 0 crc_err video input signal crc error detection. set high when a crc error is detected in the input video signal. this regist er is refreshed on every video frame. 5r 0 crc_ins video crc insertion. when set high, the luma and chroma line crc words are re-calculated and inserted into the output video signal. 4r/w 1 vm[3:0] video input format selection. see table 2. valid when "vm_sel" is high. 3-0 r/w 0 ext_sel external exth/extf input select. when set low, the exth and extf pins are configured as outputs. when set high, the GS1503 will insert trs and line numbers based on signals input at the exth and extf pins. 001 3 r/w 0 scrbypass scramble processing bypass select. when set high, the internal scrambler and nrz(i) encoder is bypassed. note: the status of the scrbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the scrbypass external pin setting. 2r/w 0 8bit_sel 8-bit input selection. when set high, the GS1503 will accept an 8-bit input video signal. 1r/w 0 dscbypass descramble process bypass select. when set high, the internal smpte 292m descrambler is bypassed. note: the status of the dscbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the dscbypass external pin setting. 0r/w 0 sw_lnb[12:0] video field 2 switching line setting. designates the video switching point for field 2. the default line number is 569, as defined by smpte 299m. 002 003 4-0 7-0 r/w 569d sw_lna[12:0] video field 1 switching line setting. designates the video switching point for field 1. the default line number is 7, as defined by smpte 299m. 004 005 4-0 7-0 r/w 7d crc_cnt[11:0] crc error accumulation. reports the accumulated number of crc errors in one video frame. 006 007 3-0 7-0 r0 rsv not used. 008 7-5 - 0 limit_on illegal code re-mappi ng select. when set high, input video words between 000-003 are re- mapped to 004, and values between 3fc-3ff are re-mapped to 3fb. valid only when "ext_sel" is set high. 4r/w 0 vblk_ins vertical blanking enable. when set high, the output video vertical blanking will be set to 040h for the luma channel and 200h for the chroma channel. 3r/w 0
15879 - 4 35 of 83 GS1503 hblk_ins horizontal blanking enable. when set high, the output video horizontal bl anking, including trs, line numbers and line crc words, will be set to 040h for the luma channel and 200h for the chroma channel. note: if blanking of line numbers and trs words is required, ln_ins and trs_ins must be set low. 2r/w 0 ln_ins line insertion enable. when set high, the GS1503 will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. 1r/w 1 trs_ins trs insertion enable. when set high, the GS1503 will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. 0r/w 1 audio am_sel audio input format (external pin/register) configuration select. when set low, the audio input format is configured via the am[1:0] pins. when set high, the audio input format is configured via the "am[1:0]" bits. 010 7 r/w 0 aud7/8_det ch7/8 audio input signal detection. when set high, an audio signal has been detected at the ain7/8 input pin. 6r 0 aud5/6_det ch5/6 audio input signal detection. when set high, an audio signal has been detected at the ain5/6 input pin. 5r 0 aud3/4_det ch3/4 audio input signal detection. when set high, an audio signal has been detected at the ain3/4 input pin. 4r 0 aud1/2_det ch1/2 audio input signal detection. when set high, an audio signal has been detected at the ain1/2 input pin. 3r 0 rsv not used. 2 - 0 am[1:0] audio input format select. see table 3. valid when "am_sel" is high. 1-0 r/w 0 table 8: multiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 36 of 83 GS1503 acrc7/8_ins ch7/8 audio channel status crc insertion. when set high, the ch7/8 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ ebu audio input format is selected. 011 7 r/w 0 acrc5/6_ins ch5/6 audio channel status crc addition. when set high, the ch5/6 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ ebu audio input format is selected. 6r/w 0 acrc3/4_ins ch3/4 audio channel status crc addition. when set high, the ch3/4 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ ebu audio input format is selected. 5r/w 0 acrc1/2_ins ch1/2 audio channel status crc addition. when set high, the ch1/2 audio input channel status crc is re-calculated before being multiplexed into the audio data packet. valid only when aes/ ebu audio input format is selected. 4r/w 0 acs7/8_err ch7/8 audio channel status error detection. when set high, a channel status crc error has been detected in the ch7/8 audio input. valid only when aes/ebu audio input format is selected. 3r 0 acs5/6_err ch5/6 audio channel status error detection. when set high, a channel status crc error has been detected in the ch5/6 audio input. valid only when aes/ebu audio input format is selected. 2r 0 acs3/4_err ch3/4 audio channel status error detection. when set high, a channel status crc error has been detected in the ch3/4 audio input. valid only when aes/ebu audio input format is selected. 1r 0 acs1/2_err ch1/2 audio channel status error detection. when set high, a channel status crc error has been detected in the ch1/2 audio input. valid only when aes/ebu audio input format is selected. 0r 0 ap7/8_err ch7/8 audio parity error detection. when set high, an audio parity error has been detected in the ch7/8 audio input. valid only when aes/ebu audio input format is selected. 012 3 r 0 ap5/6_err ch5/6 audio parity error detection. when set high, an audio parity error has been detected in the ch5/6 audio input. valid only when aes/ebu audio input format is selected. 2r 0 ap3/4_err ch3/4 audio parity error detection. when set high, an audio parity error has been detected in the ch3/4 audio input. valid only when aes/ebu audio input format is selected. 1r 0 ap1/2_err ch1/2 audio parity error detection. when set high, an audio parity error has been detected in the ch1/2 audio input. valid only when aes/ebu audio input format is selected. 0r 0 audio channel status block audio_cs[7:0] : audio_cs [183:176] audio channel status set. valid in serial audio input modes. used to enter the 23 8-bit bytes of the audio channel status block, as defined in aes3-1992. note: the crc byte is generated internally by the GS1503. 058 : 06e 7-0 : 7-0 r/w see ta b l e 9 table 8: multiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 37 of 83 GS1503 audio data packet chact[7-0] audio channel multiplex enable. when set high, the corresponding audio channel is multiplexed into the chroma video data stream. "chact[7]" corresponds to audio input channel 8 and "chact[0]" corresponds to audio input channel 1. when all bits are set low, no audio data packets will be multiplexed and the GS1503 will be in bypass mode. 013 7-0 r/w ffh cascade cascade select. when set high, the GS1503 will default to audio groups 3 and 4. when set low, the GS1503 will default to audio groups 1 and 2. note: the status of the cascade external pin is not updated in this register. the value programmed in this register is logical or'd with the cascade external pin setting. 014 7 r/w 0 rsv not used. 6 - - amuteb ch5-8 audio mute enable. when set high, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 5r/w 0 amutea ch1-4 audio mute enable. when set high, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 4r/w 0 dataidb[1:0] ch5-8 audio group did setting. designates the audio group did for audio channels 5 to 8. see table 5. when cascade (external pin or register) is set low, the default setting is audio group 2. when cascade is set high, the default setting is audio group 4. 3-2 r/w 10b dataida[1:0] ch1-4 audio group did setting. designates the audio group did for audio channels 1 to 4. see table 5. when cascade (external pin or register) is set low, the default setting is audio group 1. when cascade is set high, the default setting is audio group 3. 1-0 r/w 11b audio control packet rsv not used. 020 7-3 - 0 ctronb ch5-8 audio control packet multiplex enable. when set high, the audio control packets for audio channels 5 to 8 will be multiplexed into the luma channel of the video data stream. 2r/w 1 ctridb[1:0] ch5-8 audio control packet did setting. designates the audio control packet did for audio channels 5 to 8. see table 7. the default setting is audio group 2. 1-0 r/w 10b table 8: multiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 38 of 83 GS1503 af_nob[8:0] ch5-8 audio frame number. designates the audio frame number for audio channels 5 to 8. will be multiplexed into the audio control packet as per smpte 299m. 021 022 0 7-0 r/w 0 rateb[2:0] ch5-8 sampling frequency set. designates the audio sampling frequency for audio channels 5 to 8. will be multiplexed into the rate word of the audio control packet as per smpte 299m. the default setting is 48khz. 023 3-1 r/w 0 asxb ch5-8 synchronization set. when set high, the "asx" bit of the audio control packet rate word designates audio channels 5 to 8 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio (default setting). 0r/w 0 del1-2b[25:0] ch5/6 delay data. designates the accumulated audio processing delay relative to video for audio channels 5 and 6. will be multiplexed into the audio control packet as per smpte 299m. 024 025 026 027 1-0 7-0 7-0 7-0 r/w 0 del3-4b[25:0] ch7/8 delay data. designates the accumulated audio processing delay relative to video for audio channels 7 and 8. will be multiplexed into the audio control packet as per smpte 299m. 028 029 02a 02b 1-0 7-0 7-0 7-0 r/w 0 rsrvb[17:0] ch5-8 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 5 to 8, as per smpte 299m. note: as these words are reserved for future use, they should be set to zero. 02c 02d 02e 1-0 7-0 7-0 r/w 0 rsv not used. 02f 7-3 - 0 ctrona ch1-4 audio control packet multiplex enable. when set high, the audio control packets for audio channels 1 to 4 will be multiplexed into the luma channel of the video data stream. 2r/w 1 ctrida[1:0] ch1-4 audio control packet did setting. designates the audio control packet did for audio channels 1 to 4. see table 7. the default setting is audio group 1. 1-0 r/w 11b af_noa[8:0] ch1-4 audio frame number. designates the audio frame number for audio channels 5 to 8. will be multiplexed into the audio control packet as per smpte 299m. 030 031 0 7-0 r/w 0 ratea[2:0] ch1-4 sampling frequency set. designates the audio sampling frequency for audio channels 1 to 4. will be multiplexed into the rate word of the audio control packet as per smpte 299m. the default setting is 48khz. 032 3-1 r/w 0 asxa ch1-4 synchronization set. when set high, the "asx" bit of the audio control packet rate word designates audio channels 1 to 4 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio (default setting). 0r/w 0 table 8: multiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 39 of 83 GS1503 del1-2a[25:0] ch1/2 delay data. designates the accumulated audio processing delay relative to video for audio channels 1 and 2. will be multiplexed into the audio control packet as per smpte 299m. 033 034 035 036 1-0 7-0 7-0 7-0 r/w 0 del3-4a[25:0] ch3/4 delay data. designates the accumulated audio processing delay relative to video for audio channels 3 and 4. will be multiplexed into the audio control packet as per smpte 299m. 037 038 039 03a 1-0 7-0 7-0 7-0 r/w 0 rsrva[17:0] ch1-4 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 1 to 4, as per smpte 299m. note: as these words are reserved for future use, they should be set to zero. 03b 03c 03d 1-0 7-0 7-0 r/w 0 arbitrary data packet arbiton arbitrary data packet multiplex. valid only when "arbitmode" is high. when set high, arbitrary data packets will be multiplexed into the luma video data stream using the host interface register settings. 050 1 r/w 0 arbitmode arbitrary packet mode select. when set high, arbitrary data packets are multiplexed using the host interface register settings. when set low, arbitrary data packets are multiplexed using the external pin inputs. 0r/w 0 arbitdid[7:0] arbitrary packet data id setting. designates the 8 lsbs of the arbitrary data packet did word. the 2 msbs are internally generated. "arbitdid[7]" is the msb and "arbitdid[0]" is the lsb. valid only when "arbitmode" is high. 051 7-0 r/w 0 arbitsdid[7:0] arbitrary packet secondary data id setting. designates the 8 lsbs of the arbitrary data packet secondary did word. the 2 msbs are internally generated. "arbitsdid[7]" is the msb and "arbitsdid[0]" is the lsb. valid only when "arbitmode" is high. 052 7-0 r/w 0 arbitdc[7:0] arbitrary packet dc setting. designates the 8 lsbs of the arbitrary data packet data count word. the 2 msbs are internally generated. "arbitdc[7]" is the msb and "arbitdc[0]" is the lsb. valid only when "arbitmode" is high. 053 7-0 r/w 0 arbitlineb[11:0] field 2 arbitrary packet multiplex line number setting. designates the field 2 video line in which the arbitrary data packets will be multiplexed. valid only when "arbitmode" is high. 054 055 3-0 7-0 r/w 0 arbitlinea[11:0] field 1 arbitrary packet multiplex line number setting. designates the field 1 video line in which the arbitrary data packets will be multiplexed. valid only when "arbitmode" is high. 056 057 3-0 7-0 r/w 0 arbitudw0 : arbitudw254 arbitrary packet user data word set. designates the 8 lsbs for each of the 255 arbitrary packet user data words. the 2 msbs are internally generated. valid only when "arbitmode" is high. 100 : 1fe 7-0 : 7-0 r/w 0 table 8: multiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 40 of 83 GS1503 table 9: audio channel status default values address value channel status 058 85 professional; valid audio; no emphasis (manual override disa bled); 48khz sampling frequency (manual override disabled). 059 08 two-channel mode (manual override disabled). 05a 2c maximum audio sample word length is 24 bits; encoded audio word length is 24-bit. others 00 -
15879 - 4 41 of 83 GS1503 2. demultiplex mode 2.1 functional overview the GS1503 hd embedded audio codec fully supports the demultiplexing of audio data packets, audio control packets and arbitrary data packets as per smpte 291m and 299m. the device can be co nfigured to operate with all video standards defined in sm pte 292m, levels a through m. the GS1503 also supports the 1080/24psf, 25psf and 30psf video formats as described in smpte rp211. the video input format can be one of the following configurations: 10-bit y and c b /c r input with trs and line numbers 20-bit scrambled input the video output format can be one of the following configurations: 20-bit scrambled output 10-bit y and c b /c r output up to a maximum of 8 channels of 48khz digital audio can be demultiplexed per device. the audio output format can be selected as either aes/ebu, or one of two serial audio data output modes. a maximum of 16 channels of audio can be demultiplexed by cascading two devices in parallel. audio control packets, as defined in smpte 299m, can also be demultiplexed to obtain information about the nature of the embedded audio data. the contents of the audio control packet are stored in re gisters of the host interface. the GS1503 will also demultiplex arbitrary data packets as defined in smpte 291m. the arbitrary data packets can serve as an auxiliary data signal for proprietary applications. the GS1503 can be configured to demultiplex arbitrary data packets and output them at dedicated external pins or via the host interface registers. up to a maximum of 255 8-bit words can be demultiplexed (excluding ancillary data flags and checksum). to use the GS1503 in demultiplex mode, set the mux /demux external pin high. 2.2 video standard the video standard is selected from the vm[3:0] external pins or vm[3:0] bits 3-0 in host interface register 000h. to configure the video standard via the host interface, vm_sel bit 7 in host interface register 000h must be set high. the GS1503 will default to the vm[3:0] external pin setting. the supported video standards are listed in table 10. . table 10: supported video standards vm [3:0] input format reference smpte document smpte 292m level 1110b 1035i (30 & 30/1.001 hz) 260m a, b 1100b 1080i (25 hz) 295m c 1000b 1080i/1080sf (30 & 30/1.001 hz) 274m, rp211 d, e 1010b 1080i/1080sf (25 hz) 274m, rp211 f 1111b 1080sf (24 & 24/1.001 hz) rp211 0010b 1080p (30 & 30/1.001 hz) 274m g, h 0100b 1080p (25 hz) 274m i 0110b 1080p (24 & 24/1.001 hz) 274m j, k 0000b 720p (60 & 60/1.001 hz) 296m l, m 0001b 720p (30 & 30/1.001 hz) 296m 0011b 720p (50 hz) 296m 0101b 720p (25 hz) 296m 0111b 720p (24 & 24/1.001 hz) 296m all other settings are reserved
15879 - 4 42 of 83 GS1503 2.3 video input format 2.3.1 20-bit scrambled input fig. 31 20-bit scrambled input configuration register settings name description address bit setting default vm_sel 0: external pin select 1: register select 000 7 1 0 vm[3:0] video formal select ion (vm[3] is msb) 3-0 see table 10 0 y/c b /c r [19:0] vin[19:0] dscbypass GS1503 register settings (default mode) name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 00 0
15879 - 4 43 of 83 GS1503 2.3.2 10-bit y and c b /c r input with trs and line numbers fig. 32 10-bit y and c b /c r input with trs and line numbers configuration fig. 33 video input format (10-bit with trs and line numbers) y[9:0] c b /c r [9:0] vin[19:10] vin[9:0] dscbypass extf exth GS1503 +3.3v vn y, c b /c r v0 video 0 3 8 4 vclk exth extf 3ff 3ff xyz 000 000 000 000 xyz 10-bit ln1 ln0 crc0 crc1 register settings name description address bit setting default ext_sel 0: exth/extf output select 1: exth/extf input select 001 3 0 0 8bit_sel 0: 10-bit mode select 1: 8-bit mode select 10 0 dscbypass 0: descrambling enabled 1: bypass descrambling 01 0
15879 - 4 44 of 83 GS1503 2.4 video output format 2.4.1 10-bit y and c b /c r output fig. 34 10-bit y and c b /c r output configuration 2.4.2 20-bit scrambled output fig. 35 20-bit scrambled output configuration register settings name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 1 0 y[9:0] c b /c r [9:0] vout[19:10] vout[9:0] scrbypass GS1503 +3.3v register settings (default mode) name description address bit setting default scrbypass 0: smpte 292m scrambling enabled 1: bypass smpte 292m scrambling 001 2 0 0 y/c b /c r [19:0] vout[19:0] scrbypass GS1503
15879 - 4 45 of 83 GS1503 2.5 video data processing 2.5.1 video signal input detection the GS1503 will set the video_det external pin high when three consecutive trs are detected in the input video signal. also, the video_det bi t of host interface register 000h is set high. 2.5.2 video input crc error detection the GS1503 will set the crc_err external pin high when a crc error is detected in the input video signal. also, the crc_err bit 5 of host interface register 000h is set high. the number of crc errors accumulated in one video frame can be read form crc_cnt[11:0] in host interface registers 006h and 007h. 2.5.3 video output crc insertion when the crc_ins bit 4 of host interface register 000h is set high, the GS1503 will re-calculate the video line crc words. the re-calculated crc words are inserted in the video output signal. when crc_ins is set low, the line crc words are not updated and existing crc words at the input of the device will be output unchanged. 2.5.4 input blanking when vblk_ins bit 3 of host interface register 008h is set high, the input video vertical blanking will be set to 040h for the luma channel and 200h for the chroma channel. when hblk_ins bit 2 of host interface register 008h is set high, the input video horizontal blanking will be set to 040h for the luma channel and 200h for the chroma channel. the trs, line number and crc words will also be set to blanking values. the blanking function is perf ormed at the output of the GS1503 video data stream. if th e hblk_ins bit is set high, any embedded audio or cont rol packets will be replaced with blanking codes. the GS1503 will demultiplex data contained in the packets, prior to the blanking function, and output at the corresponding pins. register settings name description address bit setting default video_det video input signal detection (1: detection) 000 6 - 0 register settings name description address bit setting default crc_err video input signal crc erro r detection (1: detection) 000 5 - 0 crc_cnt[11:0] video input signal cr c error accumulation in 1 video frame 006 007 3-0 7-0 -0 register settings name description address bit setting default crc_ins video line crc insertion (1: insertion) 000 4 1 1
15879 - 4 46 of 83 GS1503 2.5.5 line number insertion when ln_ins bit 1 of host interface register 008h is set high, the GS1503 will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. 2.5.6 trs word insertion when trs_ins bit 0 of host interface register 008h is set high, the GS1503 will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. register settings name description address bit setting default vblk_ins input vertical blanking (1: enabled) 008 3 1 0 hblk_ins input horizontal blanking (1: enabled) 2 1 0 register settings name description address bit setting default ln_ins line number insertion (1: enabled) 008 1 1 1 register settings name description address bit setting default trs_ins trs word insertion (1: enabled) 008 0 1 1
15879 - 4 47 of 83 GS1503 2.6 audio data processing 2.6.1 digital audio output format the GS1503 has two audio output formats, aes/ebu digital audio output and serial output , as listed in table 11. the serial audio output can be formatted in the following two modes. see figure 36: 24-bit left justified; msb first 24-bit right just ified; msb last the audio output format is configured using the am[1:0] external pins or via am[1:0] bits 1-0 in host interface register 010h. to configure the audio output format via the host interface, am_sel bit 7 in host interface register 010h must be set high. the GS1503 will default to the am[1:0] external pin setting. note: when configured in aes/ebu audio mode, the GS1503 will not output a 48khz (fs) word clock at the wcouta and wcoutb pins. fig. 36 audio output formats table 11: audio output formats am[1:0] audio output format 0 serial audio output: 24-bit left justified; msb first 1 serial audio output: 24-bit right justified; msb last 2 aes/ebu audio output register settings name description address bit setting default am_sel 0: external pin setting 1: register setting 010 7 1 0 am[1:0] audio output format se lection (am[1] is msb) 1-0 see table 11 0 23 channel 1 msb channel 2 wcouta/wcoutb 0 0 lsb 23 23 msb 0 0 lsb 23 mode1 mode0 mode2 (aes/ebu) sync preamble 24-bit audio sample word vucp 0 3 4 2728293031 channel status bit validity bit user data bit parity bit sync preamble 24-bit audio sample word vucp 0 3 4 2728293031
15879 - 4 48 of 83 GS1503 2.6.2 digital audio output timing 2.6.2.1 aes/ebu format output a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. aclka is used to clock aes/ ebu digital audio signal for channels 1 to 4 (aout1/2 and aout3/4). aclkb is used to clock aes/ebu digital audio signal for channels 5 to 8 (aout5/6 and aout7/8). in aes/ ebu output mode, the audio word clock inputs wcinb and wcinb should be grounded. see figure 37 for timing . the user can access the audio channel status block information via the audio_cs[183: 0] bits in host interface registers 058h to 06eh. to r ead the audio channel status information, the cs_mode bit 3 of host interface register 06fh should be set high. the embedded audio channel from which the channel status information is to be extracted is set in the ch_ sel[2:0] bits 2-0 of host interface register 06fh. the ch_sel[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. the cs_rqst bit must be set high to begin the process of extracting the audio channel status information. once extracted, the GS1503 will set cs_wend bit high and the user can access the data for host interface registers 058h to 06eh. when cs_mode is set low, the audio channel status information in the aes/ebu aud io outputs will be replaced with data programmed in the audio_cs[183:0] bits of host interface registers 058h to 06eh. fig. 37 aes/ebu audio output configuration and timing register settings name description address bit setting default cs_wend audio channel status write flag (1: data ready) 06f 5 - 0 cs_rqst audio channel status request (1: enable) 410 cs_mode 0: audio channel status replace 1: audio channel status demultiplex 310 ch_sel[2:0] audio channel status select 2-0 - 000b y/c b /c r [19:0] vin[19:0] aout5/6 GS1503 aout1/2 aout3/4 aout7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) aclka/b aout1/2, aout3/4 aout5/6, aout7/8 6.144mhz
15879 - 4 49 of 83 GS1503 2.6.2.2 serial audio output modes a 6.144mhz (128fs) audio clock must be supplied to the aclka and aclkb inputs. an audio word clock at 48khz (fs) will be output at the wcouta and wcoutb external pins, as shown in figure 38. the user can access the audio channel status block information via the audio_cs[183: 0] bits in host interface registers 058h to 06eh. to r ead the audio channel status information, the cs_mode bit 3 of host interface register 06fh should be set high. the embedded audio channel from which the channel status information is to be extracted is set in the ch_sel[2:0] bits 2-0 of host interface register 06fh. the ch_sel[2:0] setting for audio channel 1 is 000b, through to 111b for channel 8. the cs_rqst bit must be set high to begin the process of extracting the audio channel status information. once extracted, the GS1503 will set cs_wend bit high and the user can access the data for host interface registers 058h to 06eh. when dec_mode (external pin or register setting) is set low, the audio word clock inputs wcinb and wcinb should be grounded. fig. 38 serial audio output configuration and timing y/c b /c r [19:0] vin[19:0] aout5/6 GS1503 aout1/2 aout3/4 aout7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) 6.144mhz (128 fs) aclka/b aout1/2, aout3/4 aout5/6, aout7/8 64 clks 48khz (fs) 48khz (fs) wcouta wcoutb wcouta/b 64 clks
15879 - 4 50 of 83 GS1503 2.6.3 audio clock phase locked loop figure 39 shows the configuration for deriving the 6.144mhz audio clock in aes/ ebu and serial audio output modes. the GS1503 will internally synchronize the audio output to the corresponding ac lk. this configuration is not required when dec_mode is set high. see the reference design section 3 for circuit specifics . fig. 39 block diagram of GS1503 audio clock pll 2.6.4 audio data packet detection the audio data packet detect registers will be set high when a corresponding audio group did has been detected in the chroma channel of the input video stream. host interface register 013h, bits 7-4, report the individual audio groups detected. y/c b /c r [19:0] vin[19:0] aout5/6 GS1503 aout1/2 aout3/4 aout7/8 aclka aclkb audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 6.144mhz (128 fs) pllcnta pllcntb low pass filter low pass filter vcxo 24.576mhz vcxo 24.576mhz 4 4 6.144mhz (128 fs) register settings name description address bit setting default adpg4_det audio group 4 data packet detection (1:detection) 013 7 - 0 adpg3_det audio group 3 data packet detection (1:detection) 6 - 0 adpg2_det audio group 2 data packet detection (1:detection) 5 - 0 adpg1_det audio group 1 data packet detection (1:detection) 4 - 0
15879 - 4 51 of 83 GS1503 2.6.5 ecc error detection & correction the GS1503 performs bch(31,25) forward error detection and correction as described in smpte 299m. the error correction for audio data pack ets with audio group did set in dataida[1:0] is activated when ecca_on bit 0 of host interface register 013h is set high. similarly, error correction for audio data pack ets with audio group did set in dataidb[1:0] is activated when eccb_on bit 1 of host interface register 013h is set high when a one-bit error is detect ed in a bit array of the ecc protected region of the audio data packet with audio group did set in dataida[1:0], ecca_err bit 1 in host interface register 015h is set high. when a one-bit error is detected in the ecc protected region of the audio data packet with audio group did set in dataidb[1:0], the eccb_err bit 5 in host interface register 015h is set high. in both cases, the error external pin will also be set high. a bit array is defined as all 24 bits of bit 0. the next bit array is all 24 bits of bit 1, and so on through to bit 7. up to 8 bits in error can be corrected, providing each bit error is in a different bit array. when there are two bits in error in the same 24-bit array, the errors will be detected, but not corrected. when there are more than two bits in error in a single bit array, the errors wi ll not be detected or corrected. the number of audio data pa ckets corrected in one video frame will be reported in the corresponding host interface registers correcta[11:0] and correctb[11:0]. the GS1503 will also report the number of audio data packets which could not be corrected in one video frame in the corresponding host interface registers no_correcta[11:0] and no_correctb[11:0]. 2.6.6 audio data packet error detection when the 1-255 count sequence in the data block number (dbn) word of audio data p ackets with audio group did set in dataida[1:0] is discon tinuous, the dbna_err bit 3 of host interface register 015h will be set high. when the1- 255 count sequence in the dbn word of audio data packets with audio group did set in da taidb[1:0] is discontinuous, the dbnb_err bit 7 of host interface register 015h will be set high. the GS1503 will check the parity (bit 8) for the clk, ch1-4 and ecc0-5 words in the em bedded audio data packets. when a parity bit error is detected in audio data packets with audio group did set in dataida[1:0], the adpb8a_err bit 2 of host interface register 015h will be set high. when a parity bit error is detected in audio data packets with audio group did set in dataidb[1:0], the adpb8b_err bit 6 of host interface register 015h will be set high. the GS1503 will re-calculate the audio data packets checksum and compare against the embedded checksum word. when a checksum error is detected in audio data packets with audio group did set in dataida[1:0], the adpcsa_err bit 0 of host interface register 015h will be set high. when a checksum error is detected in audio data packets with audio group did set in dataidb[1:0], the adpcsb_err bit 4 of host interface register 015h will be set high. when any of the above erro rs are detected, the error external pin will also be set high. register settings name description address bit setting default eccb_err ch5-8 audio data packet ecc error detection (1: detection) 015 5 - 0 ecca_err ch1-4 audio data packet ecc error detection (1: detection) 1- 0 correctb[11:0] ch5-8 correctable packets in one video frame 016 017 3-0 7-0 -0 no_correctb[11:0] ch5-8 un-correctab le packets in one video frame 018 019 3-0 7-0 -0 correcta[11:0] ch1-4 correctable packets in one video frame 01a 01b 3-0 7-0 -0 no_correcta[11:0] ch5-8 un-correctab le packets in one video frame 01c 01d 3-0 7-0 -0 eccb_on ch5-8 audio data packet error correction (1: on) 013 1 1 1 ecca_on ch1-4 audio data packet error correction (1: on) 0 1 1
15879 - 4 52 of 83 GS1503 2.6.7 audio data packet did setting the audio group did for audio output channels 1 to 4 (aout1/2 and aout3/4) is set in dataida[1:0] bits 1-0 of host interface register 014h. the audio group did for audio output channels 5 to 8 (aout5/6 and aout7/8) is set in dataidb[1:0] bits 3-2 of host interface register 014h. table 12 shows the 2-bit host interface setting for the corresponding audio group did. when cascade is set low (ext ernal pin or register), the GS1503 will default to audio groups 1 and 2, where aout1/ 2 and aout3/4 will be demultiplexed from audio data packets with group 1 did, an d aout5/6 and aout7/8 will be demultiplexed from audio data packets with group 2 did. when cascade is set high (external pin or register), the GS1503 will default to audio groups 3 and 4, where aout1/2 and aout3/4 will be demultiplexed from audio data packets with group 3 di d, and aout5/6 and aout7/8 will be demultiplexed from audio data packets with group 4 did. register settings name description address bit setting default dbnb_err ch5-8 audio data packet dbn error detection (1:detection) 015 7 - 0 adpb8b_err ch5-8 audio data p acket bit8 error detection (1:detection) 6- 0 adpcsb_err ch5-8 audio data packet cs error detection (1:detection) 4- 0 dbna_err ch1-4 audio data packet dbn error detection (1:detection) 3- 0 adpb8a_err ch1-4 audio data p acket bit8 error detection (1:detection) 2- 0 adpcsa_err ch1-4 audio data packet cs error detection (1:detection) 0- 0 table 12: audio group did host interface settings audio group 10-bit data host interface register setting (2-bit) 1 2e7h 11b 2 1e6h 10b 3 1e5h 01b 4 2e4h 00b register settings (cascade set low) name description address bit setting default dataida[1-0] ch1-4 audio data packet did setting 014 1-0 see ta b l e 1 2 11b dataidb[1-0] ch5-8 audio data packet did setting 3-2 10b register settings (cascade set high) name description address bit setting default dataida[1-0] ch1-4 audio data packet did setting 014 1-0 see table 12 01b dataidb[1-0] ch5-8 audio data packet did setting 3-2 00b
15879 - 4 53 of 83 GS1503 2.7 demultiplex cascade mode two GS1503 devices can be cascaded in parallel to allow up to 16 channels of audio to be demultiplexed (only one device requires cascade to be set high). figure 40 shows the cascade architecture for a 16-channel system. to configure the GS1503 for cascade mode, the cascade external pin or cascade bit 7 of host interface register 014h is set high. when set high, the GS1503 will default to audio groups 3 and 4. when set low, the GS1503 will default to audio groups 1 and 2. fig. 40 demultiplexing 16 channels of audio using cascade architecture 2.8 audio control packets 2.8.1 audio control packet detection the audio control packet detect registers will be set high when a corresponding audio group did has been detected in the luma channel of the input video stream. host interface register 020h, bits 7-4, report the individual audio groups detected. 2.8.2 audio control packet did setting to demultiplex audio control packets for audio channels 1 to 4 (aout1/2 and aout3/4), the ctrona bit 2 of host interface register 02fh is set high. to demultiplex audio control packets for audio channels 5 to 8 (aout5/6 and aout7/8), the ctronb bit 2 of host interface register 020h is set high. register settings name description address bit setting default cascade cascade enable (1: enabled) 014 7 1 0 y/c b /c r [19:0] vin[19:0] aout5/6 GS1503 aout7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 cascade vout[19:0] audio group 1 audio group 2 aout1/2 aout3/4 y/c b /c r [19:0] vin[19:0] aout5/6 GS1503 aout7/8 audio channels 9 & 10 audio channels 11 & 12 audio channels 13 & 14 audio channels 15 & 16 cascade vout[19:0] audio group 3 audio group 4 aout1/2 aout3/4 y/c b /c r [19:0] +3.3v
15879 - 4 54 of 83 GS1503 the audio control packet group did for audio output channels 1 to 4 is set in ctrida[1:0] bits 1-0 of host interface register 02fh. the au dio control packet group did for audio output channels 5 to 8 is set in ctridb[1:0] bits 3-2 of host interface register 020h. table 13 shows the 2-bit host interface setting for the corresponding audio control packet group did. when cascade is set low (ext ernal pin or register), the GS1503 will default to audio groups 1 and 2, where audio control packet data for channels 1 to 4 will be demultiplexed from packets wi th group 1 did, and audio control packet data for channels 5 to 8 will be demultiplexed from packets with group 2 did. control packet data is accessible via the corresponding registers in the host interface. register settings name description address bit setting default acpg4_det audio group 4 control packet detection (1: detection) 020 7 - 0 acpg3_det audio group 3 control packet detection (1: detection) 6 - 0 acpg2_det audio group 2 control packet detection (1: detection) 5 - 0 acpg1_det audio group 1 control packet detection (1: detection) 4 - 0 table 13: audio control packet group did host interface settings audio group 10-bit data host interface register setting (2-bit) 1 1e3h 11b 2 2e2h 10b 3 2e1h 01b 4 1e0h 00b register settings name description address bit setting default ctrona ch1-4 audio control packet demultiplex enable (1: enabled) 02f 2 1 1 ctrida[1:0] ch1-4 audio control packet did set 1-0 see table 13 11b af_noa[8:0] ch1-4 audio frame number 030 031 0 7-0 0 ratea[2:0] ch1-4 sampling frequency data 032 3-1 - 0 asxa ch1-4 synchronization (0: synchronous; 1: non-synchronous) 0- 0 del1-2a[25:0] ch1/2 delay data 033 034 035 036 1-0 7-0 7-0 7-0 -0 del3-4a[25:0] ch3/4 delay data 037 038 039 03a 1-0 7-0 7-0 7-0 -0 rsrva[17:0] ch1-4 reserved words 03b 03c 03d 1-0 7-0 7-0 -0
15879 - 4 55 of 83 GS1503 ctronb ch5-8 audio control packet demultiplex enable (1: enabled) 020 2 1 1 ctridb[1:0] ch5-8 audio control packet did set 1-0 see table 13 10b af_nob[8:0] ch5-8 audio frame number 021 022 0 7-0 -0 rateb[2:0] ch5-8 sampling frequency data 023 3-1 - 0 asxb ch5-8 synchronization (0: synchronous; 1: non-synchronous) 0- 0 del1-2b[25:0] ch5/6 delay data 024 025 026 027 1-0 7-0 7-0 7-0 -0 del3-4b[25:0] ch7/8 delay data 028 029 02a 02b 1-0 7-0 7-0 7-0 -0 rsrvb[17:0] ch5-8 reserved words 02c 02d 02e 1-0 7-0 7-0 -0 register settings name description address bit setting default
15879 - 4 56 of 83 GS1503 2.9 arbitrary data packets the GS1503 can demultiplex arbitrary data packets according to smpte 291m. typi cally, arbitrary data packets consist of linear time code (ltc), vertical interval time code (vitc) or other user data, which is multiplexed once per video field. the GS1503 has two modes in which arbitrary data can be demultiplexed from the luma channel of the video data stream. a maximum of 255 user data words can be demultiplexed. figure 41 shows the structure of the arbitrary data packet. fig. 41 arbitrary data packet structure 2.9.1 arbitrary data demultiplexing in external pin mode this is the default mode for demultiplexing arbitrary data packets. the GS1503 will set the pkten external pin high before arbitrary data will be output. two vclk cycles after pkten goes high, arbitrary data is output on the pkt[7:0] bus. see figure 42 for timing. the following arbitrary data is output on the pkt[7:0] bus: data id (did), secondary data id (sdid), data count (dc) and user data words (udw: up to a maximum of 255 words). fig. 42 arbitrary data packet output timing diagram adf user data words msb did sdid dc udw0[100] cs contents available in host interface registers udw254[1fe] udw253[1fd] udw252[1fc] udw251[1fb] udw1[101] udw2[102] udw3[103] lsb not b8 parity bit y/c b /c r [19:0] vin[19:0] GS1503 pkten pkt[7:0] arbitrary data output enable arbitrary data vclk pkt[7:0] 2 clks 2 clks arbitrary data pkten udw254 udw253 udw252 udw251 udw250 cs udw3 udw2 udw1 udw0 dc sdid did adf adf adf arbitrary packet
15879 - 4 57 of 83 GS1503 2.9.2 arbitrary data demultiplexing in host interface mode to select this mode, set arbitm ode bit 0 in host interface register 050h high. in this mode, the did, sdid, dc and user data words must be programmed in the corresponding host interface registers. set the video line number for field 1 and field 2 from which the arbitrary data packets are to be demultiplexed using the arbitlinea[11:0] an d arbitlineb[11:0] host interface registers respectively. the arbitrary data packet is demultiplexed when the arbiton bit 1 in host interface register 050h is set high. arbiton should be set low when reading the arbitrary data packet user data words from the arbitudw host interface registers. 2.10 ancillary data deletion the GS1503 can be configured to delete the embedded ancillary data packets, after demultiplexing. there are two modes for ancillary data deletion. 2.10.1 entire ancillary data deletion when the anci external pin or anci bit 1 of host interface register 040h is set high, all ancillary data packets in both the luma and chroma channel of the input video stream are deleted. the data is replaced with blanking values 040h in the luma channel and 200h in the chroma channel. the del_sel bit 0 of host interface register 040h must be set low. register settings name description address bit setting default arbiton arbitrary packet demultiplex enable (1: enabled) valid only when arbitmode is high 050 1 1 0 arbitmode arbitrary packet mode selection (0: external pin mode; 1: host mode) 01 0 arbitdid[7-0] arbitrary packet did setting 051 7-0 - 0 arbitsdid[7-0] arbitrary packet sdid setting 052 7-0 - 0 arbitdc[7-0] arbitrary packet dc setting 053 7-0 - 0 arbitlinea[11:0] field 1 multiplexing line 054 055 3-0 7-0 -0 arbitlineb[11:0] field 2 multiplexing line 056 057 3-0 7-0 -0 arbitudw arbitrary packet udw 100-1fe 7-0 - 0
15879 - 4 58 of 83 GS1503 2.10.2 audio group designation ancillary data deletion when the anci bit 1 of host interface register 040h is set high, and del_sel bit 0 of host interface register 040h is high, only audio data and control packets which are designated in host interface registers 041h will be deleted. to delete the arbitrary data packets, the corresponding did must be set in the ndid[7:0] host interface register 042h. 2.11 demultiplex mode with word clock input some commercially available hd audio embedding modules do not encode the audio word clock phase information correctly in the clk words of the audio data packet. if this clock information is not correctly encoded, the GS1503 will not output the audio data correctly. also, the GS1503 will be unable to reproduce the 48khz audio word clock (fs) at the wcouta and wcoutb pins in serial audio output modes. if the GS1503 is to be used in conjunction with a hd audio module, which encodes audio clock phase information incorrectly, the dec_mode external pin or decmode bit 2 of host interface register 01eh must be set high. when high, an audio word clock synchronous to the original word clock used for embedding must be input at the wcina and wcinb pins. figure 43 shows a system example. when the embedded clock p hase data for audio channel 1 to 4 is detected as being in error, the muxerra bit 0 of host interface register 01eh will be set high. similarly, when the embedded clock phase data for audio channel 5 to 8 is detected as being in error, the muxerrb bit 1 of host interface register 01eh will be set high register settings name description address bit setting default anci ancillary data packet dele te (1: deletion enabled) 040 1 1 0 del_sel ancillary data packet delete mode select (0: entire data delete; 1: group designated data delete) 01 0 adpg4_del audio group 4 data packet delete (1: delete) 041 7 - 0 adpg3_del audio group 3 data packet delete (1: delete) 6 - 0 adpg2_del audio group 2 data packet delete (1: delete) 5 - 0 adpg1_del audio group 1 data packet delete (1: delete) 4 - 0 acpg4_del audio group 4 control packet delete (1: delete) 3 - 0 acpg3_del audio group 3 control packet delete (1: delete) 2 - 0 acpg2_del audio group 2 control packet delete (1: delete) 1 - 0 acpg1_del audio group 1 control packet delete (1: delete) 0 - 0 ndid[7:0] arbitrary packet did delete setting 042 7-0 - 0 register settings name description address bit setting default decmode demultiplex mode with word clock input enable (1: enabled) 01e 2 1 0 muxerrb ch5-8 embedded clock phase information error detect (1: detected) 1- 0 muxerra ch1-4 embedded clock phase information error detect (1: detected) 0- 0
15879 - 4 59 of 83 GS1503 fig. 43 demultiplex mode with 48khz word clock input system example figure 44 shows the timing relationship between the audio word clock inputs and word clock outputs when the GS1503 is configured to serial audio output mode. fig. 44 wcina/b input to wcouta/b output timing diagram aout5/6 GS1503 aout7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 vout[19:0] aout1/2 aout3/4 y/c b /c r [19:0] +3.3v y/c b /c r [19:0] vin[19:0] ain5/6 hd audio embedding module ain7/8 audio channels 1 & 2 audio channels 3 & 4 audio channels 5 & 6 audio channels 7 & 8 ain1/2 ain3/4 48khz (fs) wcina 48khz (fs) wcina mux/demux wcina wcina dec_mode aclka/b wcouta/b 1 clk wcina/b
15879 - 4 60 of 83 GS1503 table 14: demultiplex mode host interface registers control item name description address bit r/w default video vm_sel video input format (external pin/internal register) configuration select. when set low, the video input format is configured via the vm[3:0] pins. when set high, the video input format is configured via the "vm[3:0]" bits. 000 7 r/w 0 video_det video signal detection flag. set high when 3 consecutive trs are detected in the input video signal. 6r 0 crc_err video input signal crc error detection. set high when a crc error is detected in the input video signal. this register is refreshed on every video frame. 5r 0 crc_ins video crc insertion. when set high, the luma and chroma line crc words are re-calculated and inserted into the output video signal. 4r/w 1 vm[3:0] video input format selection. see table 10 . valid when "vm_sel" is high. 3-0 r/w 0 ext_sel external exth/extf input select. when set low, the exth and extf pins are configured as outputs. when set high, the GS1503 will insert trs and line numbers based on signals input at the exth and extf pins. 001 3 r/w 0 scrbypass scramble processing bypass select. when set high, the internal scrambler and nrz(i) encoder is bypassed. note: the status of the scrbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the scrbypass external pin setting. 2r/w 0 8bit_sel 8-bit input selection. when set high, the GS1503 will accept an 8-bit input video signal. 1r/w 0 dscbypass descramble process bypass select. when set high, the internal smpte 292m descrambler is bypassed. note: the status of the dscbypass external pin is not updated in this register. the value programmed in this register is logical or'd with the dscbypass external pin setting. 0r/w 0 crc_cnt[11:0] crc error accumulati on. reports the accumulated number of crc errors in one video frame. 006 007 3-0 7-0 r0 rsv not used. 008 7-4 r/w 0 vblk_ins vertical blanking enable. when set high, the output video vertical blanking will be set to 040h for the luma channel and 200h for the chroma channel. 3r/w 0 hblk_ins horizontal blanking enable. when set high, the output video horizontal bl anking, including trs, line numbers and line crc words, will be set to 040h for the luma channel and 200h for the chroma channel. note: if blanking of line numbers and trs words is required, ln_ins and trs_ins must be set low. 2r/w 0
15879 - 4 61 of 83 GS1503 ln_ins line insertion enable. when set high, the GS1503 will insert line numbers into the video data stream. when set low, existing line numbers will remain in the output video stream. 1r/w 1 trs_ins trs insertion enable. when set high, the GS1503 will insert trs codes into the video data stream. when set low, existing trs codes will remain in the output video stream. 0r/w 1 audio am_sel audio input format (external pin/register) configuration select. when set low, the audio input format is configured via the am[1:0] pins. when set high, the audio input format is configured via the "am[1:0]" bits. 010 7 r/w 0 rsv not used. 6-2 - 0 am[1:0] audio input format select. see table 11 . valid when "am_sel" is high. 1-0 r/w 0 rsv not used. 01e 7-3 - 0 decmode demultiplex mode select. when set high, the GS1503 requires a 48khz word clock input at wcina and wcinb. this word clock must be synchronous to the word clock used to embed the audio data. the embedded clock information in the audio data packet will be ignored. see section 2-11. note: the status of the de c_mode external pin is not updated in this register. the value programmed in this register is logical or'd with the dec_mode external pin setting. 2r/w 0 muxerrb ch5-8 audio sample clock error. when set high, the GS1503 is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 5 to 8. see section 2-11. 1r 0 muxerra ch1-4 audio sample clock error. when set high, the GS1503 is unable to recover the audio clock phase data in the embedded audio data packet for audio channels 1 to 4. see section 2-11. 0r 0 audio channel status block audio_cs[7:0] : audio_cs [183:176] audio channel status. when "cs_mode" is set high, the 23 8-bit bytes of the audio channel status block, as defined in aes3-1992, are available in these registers. valid in both aes/ebu and serial audio modes. when "cs_mode" is set low, the audio channel status information in the aes/ebu audio outputs will be replaced with data programmed in these registers. valid only in aes/ebu audio mode. 058 : 06e 7-0 : 7-0 r0 rsv not used 06f 7-6 - 0 table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 62 of 83 GS1503 cs_wend audio channel status write flag. when set high, indicates that the audio channel status information has been written into the host interface registers 058h to 06eh and can be read by the user. valid only when "cs_mode" is set high. 5r 0 cs_rqst audio channel status request. when set high, the GS1503 will read and store the audio channel status information from the audio channel set in host interface register "ch_sel[2:0]". valid only when "cs_mode" is set high. 4r/w 0 cs_mode audio channel status mode. when set high, the user can access the embedded audio channel status information from the host interface registers 058h to 06eh. valid in both aes/ebu and serial audio modes. when set low, the audio channel status information for all audio outputs will be replaced with data programmed in host interface registers 058h - 06eh. valid only in aes/ebu audio mode. 3r/w 0 ch_sel[2:0] audio channel status select. designates the embedded audio channel from which the audio channel status information will be demultiplexed. the setting 000b represent audio channel 1, through to 111b for channel 8. valid only when "cs_mode" is set high. 2-0 r/w 000b table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 63 of 83 GS1503 audio data packet adpg4_det audio group 4 data packet detect. when set high, audio data packets with group 4 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 013 7 r 0 adpg3_det audio group 3 data packet detect. when set high, audio data packets with group 3 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 6r 0 adpg2_det audio group 2 data packet detect. when set high, audio data packets with group 2 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 5r 0 adpg1_det audio group 1 data packet detect. when set high, audio data packets with group 1 did have been detected in the incoming chroma video data stream. note: once this bit has been set, it will remain set until a device reset is performed. 4r 0 rsv not used. 3-2 - 0 eccb_on ch5-8 error correction enable. when set high, the GS1503 will perform error correction on audio data packets for channels 5 to 8, based on the six ecc words. 1r/w 1 ecca_on ch1-4 error correction enable. when set high, the GS1503 will perform error correction on audio data packets for channels 1 to 4, based on the six ecc words. 0r/w 1 table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 64 of 83 GS1503 cascade cascade select. when set high, the GS1503 will default to audio groups 3 and 4. when set low, the GS1503 will default to audio groups 1 and 2. note: the status of the cascade external pin is not updated in this register. the value programmed in this register is logical or'd with the cascade external pin setting. 014 7 r/w 0 rsv not used. 6 - 0 amuteb ch5-8 audio mute enable. when set high, the multiplexed audio packets for audio channels 5 to 8 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 5r/w 0 amutea ch1-4 audio mute enable. when set high, the multiplexed audio packets for audio channels 1 to 4 are forced to zero. note: the status of the mute external pin is not updated in this register. the value programmed in this register is logical or'd with the mute external pin setting. 4r/w 0 dataidb[1:0] ch5-8 audio group did setting. designates the audio group did for audio channels 5 to 8. see table 12 . when cascade (external pin or register) is set low, the default setting is audio group 2. when cascade is set high, the default setting is audio group 4. 3-2 r/w 10b dataida[1:0] ch1-4 audio group did setting. designates the audio group did for audio channels 1 to 4. see table 12 . when cascade (external pin or register) is set low, the default setting is audio group 1. when cascade is set high, the default setting is audio group 3. 1-0 r/w 11b table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 65 of 83 GS1503 dbnb_err ch5-8 audio data packet dbn error. when set high, a data block number error has been detected in the audio data packet for audio channels 5 to 8. 015 7 r 0 adpb8b_err ch5-8 audio data packet 'bit 8' error. when set high, a 'bit 8' error has been detected in the audio data packet for audio channels 5 to 8. 6r 0 eccb_err ch5-8 audio data packet error. when set high, an error has been detected in the audio data packet for audio channels 5 to 8, based on the six ecc words. 5r 0 adpcsb_err ch5-8 audio data packet cs error. when set high, a checksum error has been detected with the audio data packet for audio channels 5 to 8. 4r 0 dbna_err ch1-4 audio data packet dbn error. when set high, a data block number error has been detected in the audio data packet for audio channels 1 to 4. 3r 0 adpb8a_err ch1-4 audio data packet 'bit 8' error. when set high, a 'bit 8' error has been detected in the audio data packet for audio channels 1 to 4. 2r 0 ecca_err ch1-4 audio data packet error. when set high, an error has been detected in the audio data packet for audio channels 1 to 4, based on the six ecc words. 1r 0 adpcsa_err ch1-4 audio data packet cs error. when set high, a checksum error has been detected with the audio data packet for audio channels 1 to 4. 0r 0 correctb [11:0] ch5-8 ecc correctable packets. designates the number of audio data packets for channels 5 to 8 that have been corrected in one video frame using the bch forward error correction system. 016 017 3-0 7-0 r0 no_correctb [11:0] ch5-8 ecc un-correctable packets. designates the number of audio data packets for channels 5 to 8 that could not be corrected in one video frame using the bch forward error correction system. 018 019 3-0 7-0 r0 correcta [11:0] ch1-4 ecc correctable packets. designates the number of audio data packets for channels 1 to 4 that have been corrected in one video frame using the bch forward error correction system. 01a 01b 3-0 7-0 r0 no_correcta [11:0] ch1-4 ecc un-correctable packets. designates the number of audio data packets for channels 1 to 4 that could not be corrected in one video frame using the bch forward error correction system. 01c 01d 3-0 7-0 r0 table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 66 of 83 GS1503 audio control packet acpg4_det audio group 4 control packet detect. when set high, audio control packets with group 4 did have been detected in the incoming luma video data stream. 020 7 r 0 acpg3_det audio group 3 control packet detect. when set high, audio control packets with group 3 did have been detected in the incoming luma video data stream. 6r 0 acpg2_det audio group 2 control packet detect. when set high, audio control packets with group 2 did have been detected in the incoming luma video data stream. 5r 0 acpg1_det audio group 1 control packet detect. when set high, audio control packets with group 1 did have been detected in the incoming luma video data stream. 4r 0 rsv not used. 3 - 0 ctronb ch5-8 audio control packet demultiplex enable. when set high, the audio control packets in the luma channel of the video data stream for audio channels 5 to 8 will be demultiplexed. 2r/w 1 ctridb[1:0] ch5-8 audio control packet did setting. designates the audio control packet did for audio channels 5 to 8. see table 13 . the default setting is audio group 2. 1-0 r/w 10b af_nob[8:0] ch5-8 audio frame number. designates the audio frame number for audio channels 5 to 8. 021 022 0 7-0 r/w 0 rateb[2:0] ch5-8 sampling frequency. designates the audio sampling frequency for audio channels 5 to 8, taken from the rate word of the audio control packet as defined in smpte 299m. 023 3-1 r/w 0 asxb ch5-8 synchronization. when set high, the "asx" bit of the audio control packet rate word designates audio channels 5 to 8 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio. 0r/w 0 del1-2b[25:0] ch5/6 delay data. designates the accumulated audio processing delay rela tive to video for audio channels 5 and 6. 024 025 026 027 1-0 7-0 7-0 7-0 r/w 0 del3-4b[25:0] ch7/8 delay data. designates the accumulated audio processing delay rela tive to video for audio channels 7 and 8. 028 029 02a 02b 1-0 7-0 7-0 7-0 r/w 0 rsrvb[17:0] ch5-8 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 5 to 8, as per smpte 299m. 02c 02d 02e 1-0 7-0 7-0 r/w 0 table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 67 of 83 GS1503 rsv not used. 02f 7-3 - 0 ctrona ch1-4 audio control packet demultiplex enable. when set high, the audio control packets in the luma channel of the video data stream for audio channels 1 to 4 will be demultiplexed. 2r/w 1 ctrida[1:0] ch1-4 audio control packet did setting. designates the audio control packet did for audio channels 1 to 4. see table 13 . the default setting is audio group 1. 1-0 r/w 11b af_noa[8:0] ch1-4 audio frame number. designates the audio frame number for audio channels 1 to 4. 030 031 0 7-0 r/w 0 ratea[2:0] ch1-4 sampling frequency. designates the audio sampling frequency for audio channels 1 to 4, taken from the rate word of the audio control packet as defined in smpte 299m. 032 3-1 r/w 0 asxa ch1-4 synchronization. when set high, the "asx" bit of the audio control packet rate word designates audio channels 1 to 4 as asynchronous, as per smpte 299m. when set low, the "asx" bit of the audio control packet rate word designates synchronous audio. 0r/w 0 del1-2a[25:0] ch1/2 delay data. designates the accumulated audio processing delay rela tive to video for audio channels 1 and 2. 033 034 035 036 1-0 7-0 7-0 7-0 r/w 0 del3-4a[25:0] ch3/4 delay data. designates the accumulated audio processing delay rela tive to video for audio channels 3 and 4. 037 038 039 03a 1-0 7-0 7-0 7-0 r/w 0 rsrva[17:0] ch1-4 reserve words. designates the value set in the rsrv words of the audio control packet for audio channels 1 to 4, as per smpte 299m. 03b 03c 03d 1-0 7-0 7-0 r/w 0 packet delete rsv not used. 040 7-2 - 0 anci ancillary data delete. when set high, all ancillary data packets ("del_sel" is low) or ancillary data packets with dids designated in host interface registers 041h and 042h ("del_sel" is high) are removed from the video signal. the ancillary data packets are replaced with blanking codes. the data contained in the packets are output at the corresponding pins. when set low, all ancillary data packets remain in the video signal. note: the status of the anci external pin is not updated in this register. the value programmed in this register is logical or'd with the anci external pin setting 1r/w 0 del_sel ancillary data delete mode select. when set high, individual audio groups can be deleted from the video signal by programming host interface register 041h. when set low, all ancillary data packets are deleted from the video signal. 0r/w 0 table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 68 of 83 GS1503 adpg4_del audio group 4 data packet delete. when set high, all audio data packets with group 4 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 041 7 r/w 0 adpg3_del audio group 3 data packet delete. when set high, all audio data packets with group 3 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 6r/w 0 adpg2_del audio group 2 data packet delete. when set high, all audio data packets with group 2 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 5r/w 0 adpg1_del audio group 1 data packet delete. when set high, all audio data packets with group 1 did will be deleted from the chroma video data stream. valid only when "del_sel" is high. 4r/w 0 acpg4_del audio group 4 control packet delete. when set high, all audio control packets with group 4 did will be deleted from the luma video data stream. valid only when "del_sel" is set high. to be fixed. 3r/w 0 acpg3_del audio group 3 control packet delete. when set high, all audio control packets with group 3 did will be deleted from the luma video data stream. valid only when "del_sel" is high. to be fixed. 2r/w 0 acpg2_del audio group 2 control packet delete. when set high, all audio control packets with group 2 did will be deleted from the luma video data stream. valid only when "del_sel" is high. to be fixed. 1r/w 0 acpg1_del audio group 1 control packet delete. when set high, all audio control packets with group 1 did will be deleted from the luma video data stream. valid only when "del_sel" is high. to be fixed. 0r/w 0 ndid[7:0] arbitrary data packet delete. designates the did for the arbitrary data packets to be deleted from the luma video data stream. valid only when "del_sel" is high. 042 7-0 r/w 0 table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 69 of 83 GS1503 arbitrary data packet arbiton arbitrary data packet demultiplex. valid only when "arbitmode" is high. when set high, arbitrary data packets will be demultiplexed from the luma video data stream. must be set low again to access valid data in the "arbitudw" registers. 050 1 r/w 0 arbitmode arbitrary packet mode select. when set high, arbitrary data packets are demultiplexed and the user data words are stored in host interface registers 100h to 1feh. no data will be output on the pkt[7:0] external pins and ptkten will be low. when set low, arbitrary data packets are demultiplexed and output at the pkt[7:0] external pins. 0r/w 0 arbitdid[7:0] arbitrary packet data id setting. designates the 8 lsbs of the did word of the arbitrary data packet to be demultiplexed. the 2 msbs are internally generated. "arbitdid[7]" is the msb and "arbitdid[0]" is the lsb. valid only when "arbitmode" is high. 051 7-0 r/w 0 arbitsdid[7:0] arbitrary packet secondary data id setting. designates the 8 lsbs of the secondary did word of the arbitrary data packet to be demultiplexed. the 2 msbs are internally generated. "arbitsdid[7]" is the msb and "arbitsdid[0]" is the lsb. valid only when "arbitmode" is high. 052 7-0 r/w 0 arbitdc[7:0] arbitrary packet dc setting. designates the 8 lsbs of the data count word of the arbitrary data packet to be demultiplexed. the 2 msbs are internally generated. "arbitdc[7]" is the msb and "arbitdc[0]" is the lsb. valid only when "arbitmode" is high. 053 7-0 r/w 0 arbitlineb [11:0] field 2 arbitrary packet demultiplex line number setting. designates the fi eld 2 video line from which the arbitrary data packets will be demultiplexed. valid only when "arbitmode" is high. 054 055 3-0 7-0 r/w 0 arbitlinea [11:0] field 1 arbitrary packet demultiplex line number setting. designates the fi eld 1 video line from which the arbitrary data packets will be demultiplexed. valid only when "arbitmode" is high. 056 057 3-0 7-0 r/w 0 arbitudw0 : arbitudw254 arbitrary packet user data word. designates the 8 lsbs for up to 255 arbitrary packet user data words. arbitrary data can be read from these registers once "arbiton" has been set high to low. valid only when "arbitmode" is high. 100 : 1fe 7-0 : 7-0 r/w 0 table 14: demultiplex mode host interface registers (continued) control item name description address bit r/w default
15879 - 4 70 of 83 GS1503 3. reference design 3.1 circuit schematics aesout1/2 aesout3/4 aesin1/2 aesin3/4 cpu interface sdi in sdi loop thru sdi out 1 sdi out 2 aesin5/6 aesin7/8 aesout7/8 aesout5/6 gs1545 receiver vin[19..0] vclk_1503 vclk_1522 sdi lt_sdo vclk_cpu GS1503 audio endec ain1/2 ain3/4 aout1/2 aout3/4 vin[19..0] vclk_1503 resetn vout[19..0] cpuadr[8..0] cpudat[7..0] cpucsn cpuren cpuwen ain5/6 ain7/8 aout5/6 aout7/8 gs1522 serializer vout[19..0] vclk_1522 sdo0 sdo1 misc power & reset resetn resetn vin[19..0] vclk_1503 resetn vclk_1522 cpuadr[8..0] cpudat[7..0] vout[19..0] vclk_1522 cpucsn cpuren cpuwen cpudat6 cpuadr4 cpuadr8 cpuadr6 cpudat1 cpuadr2 cpudat3 cpudat0 cpuadr[8..0] cpuadr0 cpudat5 cpudat4 cpuadr1 cpudat7 cpuadr3 cpuadr7 cpudat2 cpuadr5 cpudat[7..0] cpuren cpucsn cpuwen resetn vclk_cpu vclk_cpu vcc vcc vcc vcc a_gnd vcc vcc vcc vcc vcc j5 bnc_bcj_rpc_01 1 2 3 t3 pe-65812 1 4 8 5 r79 100r j7 bnc_bcj_rpc_01 1 2 3 r10 100r r5 100r r78 75r j6 bnc_bcj_rpc_01 1 2 3 cc v n gd r /ede a b r u4 sn75176b(r) 6 7 1 8 5 2 3 j10 bnc_bcj_rpc_01 1 2 3 j8 bnc_bcj_rpc_01 1 2 3 r7 191r t8 pe-65812 1 4 8 5 j11 bnc_bcj_rpc_01 1 2 3 r70 55r r2 191r jp1 conn 24x2 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cc v n gd r /ede a b r u2 sn75176b(r) 6 7 1 8 5 2 3 t2 pe-65812 1 4 8 5 c101 220n r71 191r t6 pe-65812 1 4 8 5 j13 bnc_bcj_rpc_01 1 2 3 r /ede cc v gnd d a b u14 sn75176b(d) 4 6 7 2 3 8 5 r /ede cc v n gd d a b u1 sn75176b(d) 4 6 7 2 3 8 5 c99 220n c4 100n t5 pe-65812 1 4 8 5 r77 55r t1 pe-65812 1 4 8 5 j1 bnc_bcj_rpc_01 1 2 3 c1 220n t7 pe-65812 1 4 8 5 r8 55r c102 100n r76 191r j3 bnc_bcj_rpc_01 1 2 3 c3 220n c100 100n r4 75r r72 55r r74 75r r6 55r r /ede cc v r /ede cc v n gd d a b u3 sn75176b(d) 4 6 7 2 3 8 5 n gd d a b u12 sn75176b(d) 4 6 7 2 3 8 5 r9 75r r73 100r cc v n gd r /ede a b r u13 sn75176b(r) 6 7 1 8 5 2 3 t4 pe-65812 1 4 8 5 j12 bnc_bcj_rpc_01 1 2 3 r1 55r r3 55r cc v n gd r / e de a b r u15 sn75176b(r) 6 7 1 8 5 2 3 j4 bnc_bcj_rpc_01 1 2 3 r75 55r j2 bnc_bcj_rpc_01 1 2 3 c2 100n
15879 - 4 71 of 83 GS1503 gs1545 vco power plane analog power plane vin15 vin3 vclkin vin7 vin12 vin17 vin5 vin9 vin8 vin13 vin14 vin10 vin1 vin11 vin19 vin6 vin4 vin2 vin16 vin[19..0] vin18 vin0 +3.3v +3.3v vcc_vco1 a_vcc vcc vcc a_vcc vcc_vco1 a_vcc vcc_vco1 vcc_vco1 vcc vcc_vco1 vcc a_gnd gnd_vco1 a_gnd a_gnd gnd_vco1 a_gnd vcc_vco1 gnd_vco1 gnd_vco1 gnd_vco1 vcc_vco1 gnd_vco1 gnd_vco1 gnd_vco1 gnd_vco1 vcc vcc a_gnd vcc vcc_vco1 a_vcc gnd_vco1 a_gnd vcc 100n c53 r52 0 q2 2n3904/to 1 3 2 10n c62 u8 gs1545 22 34 23 24 13 105 98 21 36 25 27 28 79 80 78 77 91 89 113 112 86 110 85 81 96 93 73 74 72 76 75 26 5 1 7 3 9 10 12 16 11 2 4 6 14 15 19 111 8 124 122 20 88 126 116 117 120 92 106 100 101 102 103 104 115 118 119 29 121 107 108 109 123 125 127 128 41 42 43 44 45 46 47 48 49 50 53 54 55 56 59 60 61 62 63 64 30 31 32 33 35 37 38 39 40 51 52 99 95 97 94 90 87 84 83 82 57 58 65 66 67 68 69 70 71 18 17 114 nc pclk_out nc nc eqo_vee bypass pll_lock sdo_vcc pclk_vee nc nc nc dm dm nc nc vco vco pd_vee pdsub_vee iji pd_vcc lfs lfs plcap plcap lfa lbcont lfa_vcc dft_vee lfa_vee nc mcladj nc cli nc nc nc cd eqo_vcc nc nc nc nc nc nc sdo_vee a/d nc sdi sdi sdo_en nc eqi_vee nc eqi_vcc eqi_vee nc ddi_vtt nc nc nc nc nc nc nc nc nc nc nc ddi ddi nc nc nc nc data_out0 data_out1 data_out2 data_out3 data_out4 data_out5 data_out6 data_out7 data_out8 data_out9 data_out10 data_out11 data_out12 data_out13 data_out14 data_out15 data_out16 data_out17 data_out18 data_out19 sp_vcc sp_vcc sp_vee sp_vee pclk_vcc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc sdo sdo nc c55 1u r58 0r 10n c63 r54 5k c52 10u emf3 blm11a601s c79 100n 10n c64 100n c83 c76 100n c51 10u c81 100n ic5 cdc2510c 13 24 11 12 3 4 5 8 9 15 16 23 1 2 10 14 22 17 20 21 6 7 18 19 fbin clk g fbout 1y0 1y1 1y2 1y3 1y4 1y5 1y6 avcc agnd vcc vcc vcc vcc 1y7 1y8 1y9 gnd gnd gnd gnd r65 50 c80 100n 10n c72 r64 50 r53 22k 100n c50 10n c56 l4 12n emf4 blm11a601s c71 1u c74 10u c85 4u7 r59 0r 10n c58 c68 10u c60 1u r49 0r r55 75 10n c82 l3 10n c77 10u r63 75 10n c57 r62 37r4 r56 75 10n c59 u7 go1515 1 8 4 6 3 5 7 2 vctr gnd gnd gnd vcc o/p nc gnd r57 37r5 10n c73 10n c70 c66 47p 100n c69 c67 47p r50 0r c75 100n c78 100n 1.5p c65 r61 75 10n c86 r66 53r6 0.5p c84 u9 gs1508 2 1 4 6 5 8 7 3 sdi sdi rset gnd vcc sdo sdo vee d6 2 1 r51 150 c61 1u r60 22 10n c54 vin[19..0] sdi lt_sdo vclk_1503 vclk_1522 vclk_cpu
15879 - 4 72 of 83 GS1503 place close to GS1503 input pin vm1 vm0 vm1 vm2 vin1 vin3 vin9 vin10 vin16 cpudat0 ain3/4 resetn cpudat3 vout10 mute vm0 vin4 vin15 vin18 cpudat5 cpuadr0 vclk_150 3 vout17 vout14 vin8 cpuwen cpudat7 vout15 vin6 vin7 vin11 vin19 vout12 vout7 operate ain1/2 vin12 vin14 cpuadr5 vout8 anci vin5 cpudat4 cpudat2 vout9 aclkb cpucsn cpuadr2 vin2 vout4 crc_err vm2 vin0 vout18 vout11 vm3 vin17 cpuadr8 vout16 vout13 aclka muxn/demux cpuadr1 vout19 vout6 vout0 mute anci aout1/2 vout5 vout1 pllcntb vin13 cpudat1 cpuadr4 video_det cpuren cpudat6 aout3/4 vout2 cpu_sel cpuadr6 vout3 muxn/demux vm3 cpu_sel cpuadr3 cpuadr7 error pllcnta aclka aclkb aout5/6 aout7/8 ain5/6 ain7/8 vcc vcc +3.3v vcc vcc +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v ic2a 74fct7 4 2 3 14 7 4 1 5 6 d c vcc gnd s r q q r14 1k emf1 dss310-55d-223 s 1 2 3 i g o r17 33r c16 100n c9 * c17 100n c20 100n x2 vcxo-920b1-24.576mhz 1 7 8 14 nc gnd out vcc c15 100n c18 100n ic1 GS1503 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 21 22 20 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 140 141 142 143 144 139 19 45 vcc ain7/8 ain5/6 ain3/4 ain1/2 wcinb wcina dscbypass pllcntb pllcnta cascade mute anci vcc muxn/demux gnd aclka gnd error operate gnd crc_err pkteno pkten pkt7 vcc pkt6 pkt5 pkt4 vcc pkt3 pkt2 pkt1 pkt0 gnd vcc scrbypass rsv rsv rsv rsv exth extf vout0 vout1 gnd vout2 vout3 vout4 vcc vout5 vout6 vout7 gnd vout8 vout9 vout10 vcc vout11 vout12 vout13 gnd vout14 vout15 vout16 vcc vout17 vout18 vout19 gnd vcc wcouta wcoutb aout1/2 aout3/4 aout5/6 aout7/8 gnd cpuadr8 cpuadr7 cpuadr6 vcc dec_mode gnd vclk gnd cpuadr5 cpuadr0 cpuadr1 cpuadr2 cpuadr3 cpuadr4 cpudat0 cpudat1 vcc cpudat2 cpudat3 cpudat4 cpudat5 cpudat6 cpudat7 vcc cpucsn cpuren cpuwen gnd vcc vin19 vin18 vin17 gnd vin16 vin15 vin14 vcc vin13 vin12 vin11 gnd vin10 vin9 vin8 vcc vin7 vin6 vin5 gnd vin4 vin3 vin2 vcc vin1 vin0 cpu_sel am1 am0 vm2 vm1 vm0 resetn gnd vm3 aclkb video_det r23 33r r22 10k r24 180r c7 100n c14 100n c22 100n c94 100n c95 100n c96 100n emf2 dss310-55d-223 s 1 2 3 i g o c97 100n r33 10k r21 100k c8 100n r19 10k d2 pg1101w 2 1 r12 1k ic4a 74fct7 4 2 3 14 7 4 1 5 6 d c vcc gnd s r q q r20 * c23 100n c103 10u 1 2 c104 10u 1 2 c19 100n s1 khs10 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 10 11 r16 10k c24 100n ic2b 74fct7 4 12 11 10 13 9 8 d c s r q q r15 100k c25 100n c21 100n d4 br1101w 2 1 c5 10n r32 10k c6 680p r28 10k r29 10k r26 10k d1 pg1101w 2 1 r27 10k r31 10k c12 100n r30 10k c98 100n c13 100n d3 br1101w 2 1 ic4b 74fct7 4 12 11 10 13 9 8 d c s r q q c10 10n r13 1k c11 680p x1 vcxo-920b1-24.576mhz 1 7 8 14 nc gnd out vcc + - ic6a tlc2272 3 2 1 8 4 r18 180r + - ic7a tlc2272 3 2 1 8 4 r25 10k r11 1k ain3/4 vin[19..0] ain1/2 resetn aout1/2 vclk_150 3 cpuadr[8..0] aout3/4 cpudat[7..0] vout[19..0] cpucsn cpuwen cpuren aout5/6 aout7/8 ain5/6 ain7/8
15879 - 4 73 of 83 GS1503 place close to gs1522 input pin gs1522 vco power plane vout[19..0] vout2 vout0 vout12 lock_detect vout13 vout7 vout19 vout10 vout16 vout11 vout1 vout14 vout6 vout3 vout8 vout18 vout5 vout9 vout15 vout4 vout17 vcc vcc_vco2 vcc vcc_vco2 vcc_vco2 vcc vcc vcc vcc vcc vcc vcc vcc_vco2 gnd_vco2 gnd_vco2 gnd_vco2 gnd_vco2 gnd_vco2 gnd_vco2 gnd_vco2 vcc gnd_vco2 gnd_vco2 vcc_vco2 gnd_vco2 vcc c32 10u r36 0r q1 2n3904/to 1 3 2 c49 * c44 10n c37 10n r40 53.6 c28 10u c33 1u r48 22k 100n c27 c46 10n l1 12n c48 1u c38 10n c41 4u7 c47 10n c35 10n r46 * c26 1u r34 49r9 r41 75r 10n c30 r39 37r4 u5 go1515 1 8 4 6 3 5 7 2 vctr gnd gnd gnd vcc o/p nc gnd 100n c31 r43 37r4 r44 75 u6 gs1522 21 128 127 126 125 124 123 122 119 118 115 114 113 112 111 110 107 106 105 104 103 2 22 23 24 25 45 57 17 16 15 96 94 10 13 31 1 95 18 26 28 27 29 30 59 58 44 63 55 53 54 48 49 47 64 75 74 76 77 86 78 79 82 84 87 85 90 91 92 88 89 3 4 5 6 7 8 9 11 12 14 33 19 20 32 34 35 36 37 38 39 40 41 42 43 50 51 52 56 60 61 62 65 66 67 68 69 70 71 72 73 80 81 83 97 98 99 100 101 102 108 109 116 117 120 121 93 46 vcc2 data_in0 data_in1 data_in2 data_in3 data_in4 data_in5 data_in6 data_in7 data_in8 data_in9 data_in10 data_in11 data_in12 data_in13 data_in14 data_in15 data_in16 data_in17 data_in18 data_in19 pclk_in vcc2 vcc2 vcc2 vcc2 vcc2 vcc2 reset bypass pll_lock syn_detect_disable vcc3 buf_vee xdiv20 sdo1_en vee3 vee3 vee2 vee2 vee2 vee2 vee2 vee2 vee2 rset0 rset1 a0 sdo0 sdo0 sdo0_nc sdo_nc sdo1 sdo1 osc_vee vco vco pd_vee pdsub_vee dm iji pd_vcc lfs lfs plcap plcap lfa lbcont lfa_vcc dft_vee lfa_vee nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc r38 75 r35 0r c34 1u r45 53.6 0.5p c42 0.5p c40 c43 4u7 d5 2 1 r37 0 r47 150r c39 10n l2 12n c36 10n c29 1u c45 10n r42 75r sdo0 vout[19..0] sdo1 vclk_1522
15879 - 4 74 of 83 GS1503 vcc vcc +3.3v vcc vcc vcc vcc r68 300r d7 5v pwr 2 1 u10 lm1085_m 1 2 3 adj vout vin r67 470r c92 100n c90 100n c91 100uf/6.3v r69 4k7 u11 max707 1 4 5 6 2 8 7 3 mr pfi pfo nc vcc reset reset gnd emf5 blm31p330s g 100n c93 c87 100uf/6.3v j9 lp 5.00/4/90 1 2 3 4 1 2 3 4 s2 stm1- 01 d8 3.3v pwr 2 1 c88 100n c89 100uf/6.3v resetn
15879 - 4 75 of 83 GS1503 3.2 board layouts
15879 - 4 76 of 83 GS1503
15879 - 4 77 of 83 GS1503
15879 - 4 78 of 83 GS1503
15879 - 4 79 of 83 GS1503 3.3 bill of materials item quantity reference part 1 4 c1,c3,c99,c101 220n 2 41 c2,c4,c7,c8, c12,c13,c14, c15,c16,c17, c18,c19,c20, c21,c22,c23, c24,c25,c27, c31,c50,c53, c69,c75,c76, c78,c79,c80, c81,c83,c88, c90,c92,c93,c94,c95,c96, c97,c98,c100, c102 100n 3 26 l3,c5,c10,c30,c35,c36, c37,c38,c39,c44,c45,c46, c47,c54,c56,c57,c58,c59, c62,c63,c64,c70,c72,c73, c82,c86 10n 4 2 c6,c11 680p 5 4 c9,r20,r46,c49 * 6 9 c26,c29,c33,c34,c48,c55, c60,c61,c71 1u 7 9 c28,c32,c51,c52,c68,c74, c77,c103,c104 10u 8 3 c40,c42,c84 0.5p 9 3 c41,c43,c85 4u7 10 1 c65 1.5p 11 2 c66,c67 47p 12 3 c87,c89,c91 100uf/6.3v 13 4 d1,d2,d3,d4,d5,d6,d7,d8 pg1101w 14 2 emf1,emf2 dss310-55d-223s 15 2 emf3,emf4 blm11a601s 16 1 emf5 blm31p330sg 17 1 ic1 GS1503 18 2 ic2,ic4 74fct74 19 1 ic5 cdc2510c 20 2 ic6,ic7 tlc2272 21 1 jp1 conn 24x2 22 12 j1,j2,j3,j4,j5,j6,j7,j8, j10,j11,j12,j13 bnc_bcj_rpc_01 23 1 j9 lp 5.00/4/90 24 3 l1,l2,l4 12n 25 2 q2,q1 2n3904/to 26 8 r1,r3,r6,r8,r70,r72,r75, r77 55r 27 4 r2,r7,r71,r76 191r 28 6 r4,r9,r41,r42,r74,r78 75r 29 4 r5,r10,r73,r79 100r 30 4 r11,r12,r13,r14 1k 31 2 r21,r15 100k
15879 - 4 80 of 83 GS1503 32 12 r16,r19,r22,r25,r26,r27, r28,r29,r30,r31,r32,r33 10k 33 2 r17,r23 33r 34 2 r24,r18 180r 35 3 r34,r64,r65 49r9 36 8 r35,r36,r37,r49,r50,r52,r58, r59 0r 37 6 r38,r44,r55,r56,r61,r63 75r 38 3 r39,r43,r62 37r4 39 3 r40,r45,r66 53r6 40 1 r47 150r 41 2 r53,r48 22k 42 1 r51 150r 43 1 r54 5k 44 1 r57 37r5 45 1 r60 22r 46 1 r67 470r 47 1 r68 300r 48 1 r69 4k7 49 1 s1 khs10 50 1 s2 stm1-01 51 8 t1,t2,t3,t4,t5,t6,t7,t8 pe-65812 52 4 u1,u3,u12,u14 sn75176b(d) 53 4 u2,u4,u13,u15 sn75176b(r) 54 2 u7,u5 go1515 55 1 u6 gs1522 56 1 u8 gs1545 57 1 u9 gs1508 58 1 u10 lm1085_m 59 1 u11 max707 60 2 x2,x1 vcxo-920b1-24.576mhz note: this design is recommended for reference only. the aes/ebu inputs do not utilize equalization; therefore cable length performance may be limited. for improved aes/ebu input and output performance, it is recommended that examples in the aes-3i d-2001 standard annex b are consulted. this standard includes alternative schematics for both input and output networks for 75 coaxial cable transmission. for the transmission of aes/ebu over balanced 110 twisted pair cable, using xlr type connectors, please consult the aes3-1992 standard 3.3 bill of materials (continued) item quantity reference part
15879 - 4 81 of 83 GS1503 4. references & bibliography smpte 260m-1999 1125/60 high-definition production system - digital representation and bit-parallel interface smpte 274m-1998 1920 x 1080 scanning and analog and parallel digital interfaces for multiple picture rates smpte 291m-1998 ancillary data packet and space formatting smpte 292m-1998 bit-serial digital interfac e for high-definition television systems smpte 295m-1997 1920 x 1080 50 hz - scanning and interfaces smpte 296m- 2001 1280 x 720 scanning, analog and digital representation and analog interface smpte 299m-1997 24-bit digital audio format for hdtv bit-serial interface smpte rp211-2000 implementation of 24p, 25p and 30p segmented frames for 1920 x 1080 production format aes3-1992 (ansi s4.40-1992) aes recommen ded practice for digital audio engineering - serial transmission format for two-channel linearly represented digital audio data aes-3id-2001 aes information document for digital audio engineering - transmission of aes3 formatted data by unbalanced coaxial cable ebu tech. 3250-e specification of the digital audio interface (the aes/ebu interface) (second edition 1992) society of motion picture and televi sion engineers: http://www.smpte.org audio engineering society: http://www.aes.org european broadcast union: http://www.ebu.ch
15879 - 4 82 of 83 GS1503 packaging information 108 73 72 109 144 37 36 1 22 0.4 22 0.4 20 0.1 20 0.1 1.70 max 1.40 0.1 0.5 0.2 1.0 ref 0.50 0.2 12? nom 12? nom 0? min 10? max dimensions in millimetres + 0.1 -0.05 0.1 index a view on a-a 0.125 +0.05 -0.025 144 pin lqfp (fz)
15879 - 4 83 of 83 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14 -1, nishi shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2001 gennum corporation. all rights reserved. printed in canada. www.gennum.com GS1503 revision history version ecr date changes and/or modifications 2 132133 september 2003 modified host interface regist er 014 description (multi plex mode only). added revision history. 3 133576 june 2004 fixed typing errors (page 24 and 33, table 8, and table 14). added note to section 1.11. 4 136656 may 2005 added note to section 1.6.2.2 clarifyi ng that serial audio data is clocked by the GS1503 using a 3.072mhz clock. corrected packaging information. caution electrostatic sensitive devices do not open pack ages or handle except at a static-free workstation document identification data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.

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